From patchwork Tue Feb 15 13:19:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12747078 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4BC63C433EF for ; Tue, 15 Feb 2022 13:20:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=XMWFnHL+3nVf0/my1gbk5ZEsHyWRS2BAwfMJbvux0sM=; b=3WtPvNtyTfEpHL +yjIQtBl+xXYXOE8ihYbM+32CcuRi1APmpB5/ENlZbmWRbm7R3E59XKXwcFrxgzOqPEhwD6Fuvvm2 VlYQ1aWBt/PaDp+HJDFIdsRHcXFQyjx8LZRpZAZAGqFSnGtZY/vAPTERppq4wsNuIEbJwRyFftWnt ShIiAsaibOp+SZ8GY0jPWOEqxe1hy/+QjzZMkdWxqWodFXYBeX66tyflvy0+unDubY7EDImqX7th6 bzfV5kJeSfcv+axdqWZwQdl3BRh+B9fR0Y+HZDyD2GHr5tACM9WNxRCrBDYnplsuJjQwZZgAmno8r sg5SM8jbqGC6LIWVwDGg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nJxl8-002pBI-B7; Tue, 15 Feb 2022 13:20:46 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nJxkm-002p46-Fv; Tue, 15 Feb 2022 13:20:26 +0000 X-UUID: 826be66a41fc4897969824fa6dcf279f-20220215 X-UUID: 826be66a41fc4897969824fa6dcf279f-20220215 Received: from mtkcas68.mediatek.inc [(172.29.94.19)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 180554802; Tue, 15 Feb 2022 06:20:23 -0700 Received: from mtkexhb02.mediatek.inc (172.21.101.103) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 15 Feb 2022 05:20:21 -0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkexhb02.mediatek.inc (172.21.101.103) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 15 Feb 2022 21:20:14 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 15 Feb 2022 21:20:14 +0800 From: Rex-BC Chen To: CC: , , , , , , , , , Rex-BC Chen Subject: [1/2] soc: mediatek: mmsys: add sw0_rst_offset in mmsys driver data Date: Tue, 15 Feb 2022 21:19:51 +0800 Message-ID: <20220215131952.27861-2-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220215131952.27861-1-rex-bc.chen@mediatek.com> References: <20220215131952.27861-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220215_052024_563937_770E05ED X-CRM114-Status: GOOD ( 12.94 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org There are different software reset registers for difference MTK SoCs. Therefore, we add a new variable "sw0_rst_offset" to control it. Signed-off-by: Rex-BC Chen --- drivers/soc/mediatek/mt8183-mmsys.h | 2 ++ drivers/soc/mediatek/mtk-mmsys.c | 6 ++++-- drivers/soc/mediatek/mtk-mmsys.h | 3 +-- 3 files changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/soc/mediatek/mt8183-mmsys.h b/drivers/soc/mediatek/mt8183-mmsys.h index 9dee485807c9..0c021f4b76d2 100644 --- a/drivers/soc/mediatek/mt8183-mmsys.h +++ b/drivers/soc/mediatek/mt8183-mmsys.h @@ -25,6 +25,8 @@ #define MT8183_RDMA0_SOUT_COLOR0 0x1 #define MT8183_RDMA1_SOUT_DSI0 0x1 +#define MT8183_MMSYS_SW0_RST_B 0x140 + static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = { { DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0, diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 0da25069ffb3..cab62c3eac05 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -49,12 +49,14 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { .clk_driver = "clk-mt8173-mm", .routes = mmsys_default_routing_table, .num_routes = ARRAY_SIZE(mmsys_default_routing_table), + .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B, }; static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { .clk_driver = "clk-mt8183-mm", .routes = mmsys_mt8183_routing_table, .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table), + .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B, }; static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = { @@ -128,14 +130,14 @@ static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned l spin_lock_irqsave(&mmsys->lock, flags); - reg = readl_relaxed(mmsys->regs + MMSYS_SW0_RST_B); + reg = readl_relaxed(mmsys->regs + mmsys->data->sw0_rst_offset); if (assert) reg &= ~BIT(id); else reg |= BIT(id); - writel_relaxed(reg, mmsys->regs + MMSYS_SW0_RST_B); + writel_relaxed(reg, mmsys->regs + mmsys->data->sw0_rst_offset); spin_unlock_irqrestore(&mmsys->lock, flags); diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h index 8b0ed05117ea..83320019b4cf 100644 --- a/drivers/soc/mediatek/mtk-mmsys.h +++ b/drivers/soc/mediatek/mtk-mmsys.h @@ -78,8 +78,6 @@ #define DSI_SEL_IN_RDMA 0x1 #define DSI_SEL_IN_MASK 0x1 -#define MMSYS_SW0_RST_B 0x140 - struct mtk_mmsys_routes { u32 from_comp; u32 to_comp; @@ -92,6 +90,7 @@ struct mtk_mmsys_driver_data { const char *clk_driver; const struct mtk_mmsys_routes *routes; const unsigned int num_routes; + const unsigned int sw0_rst_offset; }; /*