From patchwork Tue Mar 8 06:20:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?TmFuY3kgTGluICjmnpfmrKPonqIp?= X-Patchwork-Id: 12773095 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9BD13C433EF for ; Tue, 8 Mar 2022 06:34:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=yzuMpwABtRpNz8iVIg8GQ6s+7SYC/y+7UJRHiMNTsAs=; b=u/uTC59U3d/x+6 FSAUCdAQM11MymKh5v9KTm/A30qt9G90fNmlJCIBN1LQ0W6WHOJYDfDP5x9fRcCPVl/1YyCd66j3j bk/rzrDH+8u2z2bVUtrsWUSY6hQbno4JOnj4TFXGuYYzutDCe0XmYiOBB17M3eioTOVbJS7zmCPam yTsx9y1IqnMZ/IOg4lY7F51tcuoGcGz6b0JkN6yvaZ6QGP0aoYxornQ/7wgTKkIfarQyvnb2VBVHd ptBKQ1kBkT7aH8Xr9kCcjdcz3UrFoSgZT66cnL/gZHFOszE3XQvETsJdgSANgSxx/Dq0FYBEnJT+0 iF8Djpp7TbZenQ2Bwypw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nRTQ1-002qyV-U5; Tue, 08 Mar 2022 06:34:01 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nRTMj-002ou4-3e; Tue, 08 Mar 2022 06:30:38 +0000 X-UUID: dc23f3fc4c8f4d6aade7cf929eb5b756-20220307 X-UUID: dc23f3fc4c8f4d6aade7cf929eb5b756-20220307 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 2043944921; Mon, 07 Mar 2022 23:30:20 -0700 Received: from mtkmbs10n2.mediatek.inc (172.21.101.183) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 7 Mar 2022 22:20:20 -0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Tue, 8 Mar 2022 14:20:17 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 8 Mar 2022 14:20:17 +0800 From: Nancy.Lin To: CK Hu CC: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Matthias Brugger , "jason-jh . lin" , "Nancy . Lin" , Yongqiang Niu , , , , , , , Subject: [PATCH v13 14/22] drm/mediatek: add display merge async reset control Date: Tue, 8 Mar 2022 14:20:04 +0800 Message-ID: <20220308062012.21838-15-nancy.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220308062012.21838-1-nancy.lin@mediatek.com> References: <20220308062012.21838-1-nancy.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220307_223037_183066_C920185E X-CRM114-Status: GOOD ( 11.88 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Add merge async reset control in mtk_merge_stop. Async hw doesn't do self reset on each sof signal(start of frame), so need to reset the async to clear the hw status for the next merge start. Signed-off-by: Nancy.Lin Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_disp_merge.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c index 9dca145cfb71..177473fa8160 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_merge.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include "mtk_drm_ddp_comp.h" @@ -79,6 +80,9 @@ void mtk_merge_stop(struct device *dev) struct mtk_disp_merge *priv = dev_get_drvdata(dev); mtk_merge_stop_cmdq(dev, NULL); + + if (priv->async_clk) + device_reset_optional(dev); } void mtk_merge_start_cmdq(struct device *dev, struct cmdq_pkt *cmdq_pkt)