From patchwork Fri Mar 11 01:54:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?TmFuY3kgTGluICjmnpfmrKPonqIp?= X-Patchwork-Id: 12777295 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D3A7DC433F5 for ; Fri, 11 Mar 2022 02:10:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=mDgb54DNh0/RfphX6iO/ODe9/LBASNdX0zY7k1d10oM=; b=0jiGvS/Pjda13c nwvr1ElBngQ4R3AbJDH1Qe2IEUNvzjsR4SY84KSVQAxe6gnznIml9oYkoaKHzmFRw2XsZMps/X7ZX OLCv3rnuDmTQg8ccEA0a0bI2GjzV63ZVjPADxJgEwI63Kylff7FaUvPVVw3lchKnogovJBb5ah3ej Nb6P7wYxgXi7pIBK2kFHvrXrcU+p4ATBObHCR388gxVJ34pzZwlYtvIDituN0366MkFvE3O4m0xkV U3f3Qb/WKhMNVyjlWonk9zvGDVSqKz2LXzXOFG6PgPBaZTs0xXoCo7i8imfQPc2TWlxKuHicwR/JO o/XJ2cVAGUDICABBh9Mg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nSUjk-00EeTb-G3; Fri, 11 Mar 2022 02:10:36 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nSUbK-00EaOh-Je; Fri, 11 Mar 2022 02:01:56 +0000 X-UUID: eb5d9f97e7e44c99941336d4f611a368-20220310 X-UUID: eb5d9f97e7e44c99941336d4f611a368-20220310 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1668662009; Thu, 10 Mar 2022 19:01:45 -0700 Received: from MTKMBS07N2.mediatek.inc (172.21.101.141) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 10 Mar 2022 17:55:10 -0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 11 Mar 2022 09:55:08 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 11 Mar 2022 09:55:08 +0800 From: Nancy.Lin To: Rob Herring , Matthias Brugger , Chun-Kuang Hu , "Philipp Zabel" , , "AngeloGioacchino Del Regno" , CC: David Airlie , Daniel Vetter , "Nathan Chancellor" , Nick Desaulniers , "Nancy . Lin" , "jason-jh . lin" , Yongqiang Niu , , , , , , , , , Subject: [PATCH v15 09/22] soc: mediatek: add mtk-mutex support for mt8195 vdosys1 Date: Fri, 11 Mar 2022 09:54:53 +0800 Message-ID: <20220311015506.11232-10-nancy.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220311015506.11232-1-nancy.lin@mediatek.com> References: <20220311015506.11232-1-nancy.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220310_180154_669276_D59987CD X-CRM114-Status: GOOD ( 11.92 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Add mtk-mutex support for mt8195 vdosys1. The vdosys1 path component contains ovl_adaptor, merge5, and dp_intf1. Ovl_adaptor is composed of several sub-elements. Signed-off-by: Nancy.Lin Reviewed-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-mutex.c | 54 ++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index cb791671d751..70e6043e99df 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -129,6 +129,35 @@ #define MT8195_MUTEX_MOD_DISP_PWM0 BIT(27) #define MT8195_MUTEX_MOD_DISP_PWM1 BIT(28) +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 BIT(0) +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 BIT(1) +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 BIT(2) +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 BIT(3) +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 BIT(4) +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 BIT(5) +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 BIT(6) +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 BIT(7) +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 BIT(8) +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 BIT(9) +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 BIT(10) +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE3 BIT(11) +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE4 BIT(12) +#define MT8195_MUTEX_MOD_DISP1_VPP2_DL_RELAY BIT(13) +#define MT8195_MUTEX_MOD_DISP1_VPP3_DL_RELAY BIT(14) +#define MT8195_MUTEX_MOD_DISP1_VDO0_DSC_DL_ASYNC BIT(15) +#define MT8195_MUTEX_MOD_DISP1_VDO0_MERGE_DL_ASYNC BIT(16) +#define MT8195_MUTEX_MOD_DISP1_VDO1_OUT_DL_RELAY BIT(17) +#define MT8195_MUTEX_MOD_DISP1_DISP_MIXER BIT(18) +#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE0 BIT(19) +#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE1 BIT(20) +#define MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE0 BIT(21) +#define MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE1 BIT(22) +#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_BE0 BIT(23) +#define MT8195_MUTEX_MOD_DISP1_HDR_MLOAD BIT(24) +#define MT8195_MUTEX_MOD_DISP1_DPI0 BIT(25) +#define MT8195_MUTEX_MOD_DISP1_DPI1 BIT(26) +#define MT8195_MUTEX_MOD_DISP1_DP_INTF0 BIT(27) + #define MT2712_MUTEX_MOD_DISP_PWM2 BIT(10) #define MT2712_MUTEX_MOD_DISP_OVL0 BIT(11) #define MT2712_MUTEX_MOD_DISP_OVL1 BIT(12) @@ -332,6 +361,27 @@ static const u64 mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0, [DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0, [DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0, + [DDP_COMPONENT_OVL_ADAPTOR] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 | + MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 | + MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 | + MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 | + MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 | + MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 | + MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 | + MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 | + MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 | + MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 | + MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 | + MT8195_MUTEX_MOD_DISP1_VPP_MERGE3 | + MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE0 | + MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE1 | + MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE0 | + MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE1 | + MT8195_MUTEX_MOD_DISP1_HDR_VDO_BE0 | + MT8195_MUTEX_MOD_DISP1_HDR_MLOAD | + MT8195_MUTEX_MOD_DISP1_DISP_MIXER, + [DDP_COMPONENT_MERGE5] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE4, + [DDP_COMPONENT_DP_INTF1] = MT8195_MUTEX_MOD_DISP1_DP_INTF0, }; static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = { @@ -517,6 +567,9 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex, case DDP_COMPONENT_DP_INTF0: sof_id = MUTEX_SOF_DP_INTF0; break; + case DDP_COMPONENT_DP_INTF1: + sof_id = MUTEX_SOF_DP_INTF1; + break; default: if (mtx->data->mutex_mod[id] <= BIT(31)) { offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg, @@ -557,6 +610,7 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex, case DDP_COMPONENT_DPI0: case DDP_COMPONENT_DPI1: case DDP_COMPONENT_DP_INTF0: + case DDP_COMPONENT_DP_INTF1: writel_relaxed(MUTEX_SOF_SINGLE_MODE, mtx->regs + DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg,