From patchwork Fri Mar 11 01:54:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?TmFuY3kgTGluICjmnpfmrKPonqIp?= X-Patchwork-Id: 12777294 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CC33BC433EF for ; Fri, 11 Mar 2022 02:10:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Y1++CI+m+mBC1+w3EST3kI55pSVWQiExk9iY+37PFDo=; b=vsVQNssasQWG5Y CWPPspO5izE8xdeMP+PL1kWyDVVILYvPK/+xKsIKzji8Qy3O8VqG2PVbqi+s5Y8RDbojmvBpZvrLL eeyA36i7OHAS47G+JR5tf37TjiiMsj1jIc6B3l+FNMfg5/ugrSCtlP+kbma0W6nCWgU4/F6zbSkf5 BKM3bFookcI2FcMX+w0mBxVG25LWm1uQKzvfKAIHaEdixSf/jn67vUbMtFfAsNpKySIiwa5u9p84A bnnoaeex8ezd8JM96CDtUtzqhaFoKR34keSRiq3eFM3lJwYGvDpn8ECXTjYgnwEPJMCSaOupQaO08 7iQ5wmmKC8FiB9DN4VGQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nSUj5-00EeAa-11; Fri, 11 Mar 2022 02:09:55 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nSUbJ-00EaOU-Ek; Fri, 11 Mar 2022 02:01:55 +0000 X-UUID: ed060fe3b870404798f7464f1a8d55bb-20220310 X-UUID: ed060fe3b870404798f7464f1a8d55bb-20220310 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1683972813; Thu, 10 Mar 2022 19:01:45 -0700 Received: from MTKMBS07N2.mediatek.inc (172.21.101.141) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 10 Mar 2022 17:55:09 -0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 11 Mar 2022 09:55:08 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 11 Mar 2022 09:55:08 +0800 From: Nancy.Lin To: Rob Herring , Matthias Brugger , Chun-Kuang Hu , "Philipp Zabel" , , "AngeloGioacchino Del Regno" , CC: David Airlie , Daniel Vetter , "Nathan Chancellor" , Nick Desaulniers , "Nancy . Lin" , "jason-jh . lin" , Yongqiang Niu , , , , , , , , , Subject: [PATCH v15 06/22] soc: mediatek: add cmdq support of mtk-mmsys config API for mt8195 vdosys1 Date: Fri, 11 Mar 2022 09:54:50 +0800 Message-ID: <20220311015506.11232-7-nancy.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220311015506.11232-1-nancy.lin@mediatek.com> References: <20220311015506.11232-1-nancy.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220310_180153_527988_B87621F9 X-CRM114-Status: GOOD ( 18.65 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Add cmdq support for mtk-mmsys config API. The mmsys config register settings need to take effect with the other HW settings(like OVL_ADAPTOR...) at the same vblanking time. If we use CPU to write the mmsys reg, we can't guarantee all the settings can be written in the same vblanking time. Cmdq is used for this purpose. We prepare all the related HW settings in one cmdq packet. The first command in the packet is "wait stream done", and then following with all the HW settings. After the cmdq packet is flush to GCE HW. The GCE waits for the "stream done event" to coming and then starts flushing all the HW settings. This can guarantee all the settings flush in the same vblanking. Signed-off-by: Nancy.Lin Reviewed-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-mmsys.c | 27 +++++++++++++++++++++----- include/linux/soc/mediatek/mtk-mmsys.h | 6 +++++- 2 files changed, 27 insertions(+), 6 deletions(-) diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 6dd68483012c..c686b17ca62f 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -98,6 +98,7 @@ struct mtk_mmsys { const struct mtk_mmsys_driver_data *data; spinlock_t lock; /* protects mmsys_sw_rst_b reg */ struct reset_controller_dev rcdev; + struct cmdq_client_reg cmdq_base; }; void mtk_mmsys_ddp_connect(struct device *dev, @@ -190,7 +191,7 @@ static const struct reset_control_ops mtk_mmsys_reset_ops = { }; void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config, - u32 id, u32 val) + u32 id, u32 val, struct cmdq_pkt *cmdq_pkt) { struct mtk_mmsys *mmsys = dev_get_drvdata(dev); const struct mtk_mmsys_config *mmsys_config = mmsys->data->config; @@ -214,10 +215,19 @@ void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config, mask = mmsys_config[i].mask; reg_val = val << mmsys_config[i].shift; - tmp = readl(mmsys->regs + offset); - - tmp = (tmp & ~mask) | reg_val; - writel(tmp, mmsys->regs + offset); +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + if (cmdq_pkt && mmsys->cmdq_base.size) { + cmdq_pkt_write_mask(cmdq_pkt, mmsys->cmdq_base.subsys, + mmsys->cmdq_base.offset + offset, reg_val, + mask); + } else { +#endif + tmp = readl(mmsys->regs + offset); + tmp = (tmp & ~mask) | reg_val; + writel(tmp, mmsys->regs + offset); +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + } +#endif } EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config); @@ -253,6 +263,13 @@ static int mtk_mmsys_probe(struct platform_device *pdev) } mmsys->data = of_device_get_match_data(&pdev->dev); + +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0); + if (ret) + dev_dbg(dev, "No mediatek,gce-client-reg!\n"); +#endif + platform_set_drvdata(pdev, mmsys); clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver, diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index b2d2310d7e7a..3e998bfb795a 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -6,6 +6,10 @@ #ifndef __MTK_MMSYS_H #define __MTK_MMSYS_H +#include +#include +#include + enum mtk_ddp_comp_id; struct device; @@ -78,6 +82,6 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, enum mtk_ddp_comp_id next); void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config, - u32 id, u32 val); + u32 id, u32 val, struct cmdq_pkt *cmdq_pkt); #endif /* __MTK_MMSYS_H */