From patchwork Fri Mar 18 09:54:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Smlhbmp1biBXYW5nICjnjovlu7rlhpsp?= X-Patchwork-Id: 12785103 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8E5D0C433FE for ; Fri, 18 Mar 2022 09:57:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=9bDhgUCeZ4zMDQ8gi7KKR5RoeW1iyysUjg/IrKgxEWA=; b=OXspLtkwhp6/GQ F0AV+RSbvUvzxqZ1vrZY9WzAQZEjjC0lKDeJm+WTldOn0z9HrAgKVK9T+v9AAGP6I3kZ9tU24NrZe dK+lbFf9hrGeVaCvcOWubXvX6CrsIYjO9r+/1bkTMbSz+QRffCUytWZWYFDl0hPd3r6Re5f2/Wqr6 fmog6mucNVoe34s4KoHJX+NMAgAY1VRb/pCNOyS2QgImLMSazuI2aYQ0gQ4A83YyPAkV6c0PJ/D2A zRdiYQ4QRr9kLK55HbpyKd/y2SVpmUyAeEysXhDTPTCjMKqYwYY7bomLqUPkCVSRfrY/QX+eKuUFJ QRFkOHMdSnSFM7HgQGAw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nV9Mc-0013O0-AF; Fri, 18 Mar 2022 09:57:42 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nV9MH-0013JP-5j; Fri, 18 Mar 2022 09:57:22 +0000 X-UUID: 9385631d0e2a480fb11c0fc027196ea6-20220318 X-UUID: 9385631d0e2a480fb11c0fc027196ea6-20220318 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 938068249; Fri, 18 Mar 2022 02:57:12 -0700 Received: from mtkmbs10n2.mediatek.inc (172.21.101.183) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 18 Mar 2022 02:54:22 -0700 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Fri, 18 Mar 2022 17:54:21 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 18 Mar 2022 17:54:20 +0800 From: Jianjun Wang To: Chunfeng Yun , Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Matthias Brugger , Chen-Yu Tsai CC: Jianjun Wang , , , , , , , , , , , Subject: [PATCH v2 1/2] dt-bindings: phy: mediatek: Add YAML schema for PCIe PHY Date: Fri, 18 Mar 2022 17:54:16 +0800 Message-ID: <20220318095417.2016-2-jianjun.wang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220318095417.2016-1-jianjun.wang@mediatek.com> References: <20220318095417.2016-1-jianjun.wang@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220318_025721_233588_BB3F02BF X-CRM114-Status: GOOD ( 13.28 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Add YAML schema documentation for PCIe PHY on MediaTek chipsets. Signed-off-by: Jianjun Wang --- .../bindings/phy/mediatek,pcie-phy.yaml | 75 +++++++++++++++++++ 1 file changed, 75 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml new file mode 100644 index 000000000000..868bf976568b --- /dev/null +++ b/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/mediatek,pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek PCIe PHY + +maintainers: + - Jianjun Wang + +description: | + The PCIe PHY supports physical layer functionality for PCIe Gen3 port. + +properties: + compatible: + const: mediatek,mt8195-pcie-phy + + reg: + maxItems: 1 + + reg-names: + items: + - const: sif + + "#phy-cells": + const: 0 + + nvmem-cells: + description: + Phandles to nvmem cell that contains the efuse data, if unspecified, + default value is used. + + nvmem-cell-names: + items: + - const: glb_intr + - const: tx_ln0_pmos + - const: tx_ln0_nmos + - const: rx_ln0 + - const: tx_ln1_pmos + - const: tx_ln1_nmos + - const: rx_ln1 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - reg-names + - "#phy-cells" + - power-domains + +additionalProperties: false + +examples: + - | + phy@11e80000 { + compatible = "mediatek,mt8195-pcie-phy"; + #phy-cells = <0>; + reg = <0x11e80000 0x10000>; + reg-names = "sif"; + nvmem-cells = <&pciephy_glb_intr>, + <&pciephy_tx_ln0_pmos>, + <&pciephy_tx_ln0_nmos>, + <&pciephy_rx_ln0>, + <&pciephy_tx_ln1_pmos>, + <&pciephy_tx_ln1_nmos>, + <&pciephy_rx_ln1>; + nvmem-cell-names = "glb_intr", "tx_ln0_pmos", + "tx_ln0_nmos", "rx_ln0", + "tx_ln1_pmos", "tx_ln1_nmos", + "rx_ln1"; + power-domains = <&spm 2>; + };