| Message ID | 20220422060152.13534-14-rex-bc.chen@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Cleanup MediaTek clk reset drivers and support MT8192/MT8195 | expand |
On 22/04/2022 08:01, Rex-BC Chen wrote: > We will use the infra_ao reset which is defined in mt8195-sys-clock. > The maximum value of reset-cells is 2. Therefore, we add this patch to > define it. Same comments as your other reset patch. Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml index 57a1503d95fe..66b7852ce711 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml @@ -37,6 +37,9 @@ properties: '#clock-cells': const: 1 + '#reset-cells': + maximum: 2 + required: - compatible - reg
We will use the infra_ao reset which is defined in mt8195-sys-clock. The maximum value of reset-cells is 2. Therefore, we add this patch to define it. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> --- .../bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml | 3 +++ 1 file changed, 3 insertions(+)