| Message ID | 20220614121024.31667-2-irui.wang@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Enable two hardware jpeg encoder for MT8195 | expand |
On Tue, Jun 14, 2022 at 08:10:18PM +0800, Irui Wang wrote: > From: kyrie wu <kyrie.wu@mediatek.com> > > Add mediatek,mt8195-jpgenc compatible to binding document. > > Signed-off-by: kyrie wu <kyrie.wu@mediatek.com> > --- > .../media/mediatek,mt8195-jpegenc.yaml | 153 ++++++++++++++++++ > 1 file changed, 153 insertions(+) > create mode 100644 Documentation/devicetree/bindings/media/mediatek,mt8195-jpegenc.yaml > > diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegenc.yaml b/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegenc.yaml > new file mode 100644 > index 000000000000..a7f9f723d5db > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegenc.yaml > @@ -0,0 +1,153 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/media/mediatek,mt8195-jpegenc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek JPEG Encoder Device Tree Bindings > + > +maintainers: > + - kyrie wu <kyrie.wu@mediatek.corp-partner.google.com> > + > +description: |- > + MediaTek JPEG Encoder is the JPEG encode hardware present in MediaTek SoCs > + > +properties: > + compatible: > + items: > + - const: mediatek,mt8195-jpgenc > + > + mediatek,jpegenc-multi-core: > + type: boolean > + description: | > + Indicates whether the jpeg encoder has multiple cores or not. > + > + power-domains: > + maxItems: 1 > + > + iommus: > + maxItems: 4 > + description: | > + Points to the respective IOMMU block with master port as argument, see > + Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details. > + Ports are according to the HW. > + > + "#address-cells": > + const: 2 > + > + "#size-cells": > + const: 2 > + > + ranges: true > + > +# Required child node: > +patternProperties: > + "^jpgenc@[0-9a-f]+$": > + type: object > + description: | > + The jpeg encoder hardware device node which should be added as subnodes to > + the main jpeg node. > + > + properties: > + compatible: > + const: mediatek,mt8195-jpgenc-hw > + > + reg: > + maxItems: 1 > + > + hw_id: > + description: | > + Current jpegenc hw id. Same question here. Surely, I asked sometime in the last 8 versions, but no explanation here and I'm not going to go look for it. > + > + iommus: > + minItems: 1 > + maxItems: 32 > + description: | > + List of the hardware port in respective IOMMU block for current Socs. > + Refer to bindings/iommu/mediatek,iommu.yaml. > + > + interrupts: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > + clock-names: > + items: > + - const: jpgenc > + > + power-domains: > + maxItems: 1 > + > + required: > + - compatible > + - reg > + - hw_id > + - iommus > + - interrupts > + - clocks > + - clock-names > + - power-domains > + > + additionalProperties: false > + > +required: > + - compatible > + - power-domains > + - iommus > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/memory/mt8195-memory-port.h> > + #include <dt-bindings/interrupt-controller/irq.h> > + #include <dt-bindings/clock/mt8195-clk.h> > + #include <dt-bindings/power/mt8195-power.h> > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + jpgenc_master { > + compatible = "mediatek,mt8195-jpgenc"; > + mediatek,jpegenc-multi-core; > + power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; > + iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>, > + <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>, > + <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>, > + <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + jpgenc@1a030000 { > + compatible = "mediatek,mt8195-jpgenc-hw"; > + reg = <0 0x1a030000 0 0x10000>; > + hw_id = <0>; > + iommus = <&iommu_vdo M4U_PORT_L19_JPGENC_Y_RDMA>, > + <&iommu_vdo M4U_PORT_L19_JPGENC_C_RDMA>, > + <&iommu_vdo M4U_PORT_L19_JPGENC_Q_TABLE>, > + <&iommu_vdo M4U_PORT_L19_JPGENC_BSDMA>; > + interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&vencsys CLK_VENC_JPGENC>; > + clock-names = "jpgenc"; > + power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; > + }; > + > + jpgenc@1b030000 { > + compatible = "mediatek,mt8195-jpgenc-hw"; > + reg = <0 0x1b030000 0 0x10000>; > + hw_id = <1>; > + iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>, > + <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>, > + <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>, > + <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>; > + interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGENC>; > + clock-names = "jpgenc"; > + power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; > + }; > + }; > + }; > -- > 2.18.0 > >
On Fri, 2022-06-17 at 17:11 -0600, Rob Herring wrote: > On Tue, Jun 14, 2022 at 08:10:18PM +0800, Irui Wang wrote: > > From: kyrie wu <kyrie.wu@mediatek.com> > > > > Add mediatek,mt8195-jpgenc compatible to binding document. > > > > Signed-off-by: kyrie wu <kyrie.wu@mediatek.com> > > --- > > .../media/mediatek,mt8195-jpegenc.yaml | 153 > > ++++++++++++++++++ > > 1 file changed, 153 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/media/mediatek,mt8195- > > jpegenc.yaml > > > > diff --git > > a/Documentation/devicetree/bindings/media/mediatek,mt8195- > > jpegenc.yaml > > b/Documentation/devicetree/bindings/media/mediatek,mt8195- > > jpegenc.yaml > > new file mode 100644 > > index 000000000000..a7f9f723d5db > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/media/mediatek,mt8195- > > jpegenc.yaml > > @@ -0,0 +1,153 @@ > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: > > http://devicetree.org/schemas/media/mediatek,mt8195-jpegenc.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: MediaTek JPEG Encoder Device Tree Bindings > > + > > +maintainers: > > + - kyrie wu <kyrie.wu@mediatek.corp-partner.google.com> > > + > > +description: |- > > + MediaTek JPEG Encoder is the JPEG encode hardware present in > > MediaTek SoCs > > + > > +properties: > > + compatible: > > + items: > > + - const: mediatek,mt8195-jpgenc > > + > > + mediatek,jpegenc-multi-core: > > + type: boolean > > + description: | > > + Indicates whether the jpeg encoder has multiple cores or > > not. > > + > > + power-domains: > > + maxItems: 1 > > + > > + iommus: > > + maxItems: 4 > > + description: | > > + Points to the respective IOMMU block with master port as > > argument, see > > + Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml > > for details. > > + Ports are according to the HW. > > + > > + "#address-cells": > > + const: 2 > > + > > + "#size-cells": > > + const: 2 > > + > > + ranges: true > > + > > +# Required child node: > > +patternProperties: > > + "^jpgenc@[0-9a-f]+$": > > + type: object > > + description: | > > + The jpeg encoder hardware device node which should be added > > as subnodes to > > + the main jpeg node. > > + > > + properties: > > + compatible: > > + const: mediatek,mt8195-jpgenc-hw > > + > > + reg: > > + maxItems: 1 > > + > > + hw_id: > > + description: | > > + Current jpegenc hw id. > > Same question here. Surely, I asked sometime in the last 8 versions, > but > no explanation here and I'm not going to go look for it. Dear Rob, I'm sorry for not giving an accurate explanation in time. The MT8195 has own two encoding hardwares, we use hw_id to represent them. hw_id = 0, for hardware 0, and hw_id = 1, repesents another one. I will improve the description in the next version. Thanks. sincerely, Kyrie. > > > + > > + iommus: > > + minItems: 1 > > + maxItems: 32 > > + description: | > > + List of the hardware port in respective IOMMU block for > > current Socs. > > + Refer to bindings/iommu/mediatek,iommu.yaml. > > + > > + interrupts: > > + maxItems: 1 > > + > > + clocks: > > + maxItems: 1 > > + > > + clock-names: > > + items: > > + - const: jpgenc > > + > > + power-domains: > > + maxItems: 1 > > + > > + required: > > + - compatible > > + - reg > > + - hw_id > > + - iommus > > + - interrupts > > + - clocks > > + - clock-names > > + - power-domains > > + > > + additionalProperties: false > > + > > +required: > > + - compatible > > + - power-domains > > + - iommus > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/interrupt-controller/arm-gic.h> > > + #include <dt-bindings/memory/mt8195-memory-port.h> > > + #include <dt-bindings/interrupt-controller/irq.h> > > + #include <dt-bindings/clock/mt8195-clk.h> > > + #include <dt-bindings/power/mt8195-power.h> > > + > > + soc { > > + #address-cells = <2>; > > + #size-cells = <2>; > > + > > + jpgenc_master { > > + compatible = "mediatek,mt8195-jpgenc"; > > + mediatek,jpegenc-multi-core; > > + power-domains = <&spm > > MT8195_POWER_DOMAIN_VENC_CORE1>; > > + iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>, > > + <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>, > > + <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>, > > + <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>; > > + #address-cells = <2>; > > + #size-cells = <2>; > > + ranges; > > + > > + jpgenc@1a030000 { > > + compatible = "mediatek,mt8195-jpgenc-hw"; > > + reg = <0 0x1a030000 0 0x10000>; > > + hw_id = <0>; > > + iommus = <&iommu_vdo > > M4U_PORT_L19_JPGENC_Y_RDMA>, > > + <&iommu_vdo M4U_PORT_L19_JPGENC_C_RDMA>, > > + <&iommu_vdo M4U_PORT_L19_JPGENC_Q_TABLE>, > > + <&iommu_vdo M4U_PORT_L19_JPGENC_BSDMA>; > > + interrupts = <GIC_SPI 342 > > IRQ_TYPE_LEVEL_HIGH 0>; > > + clocks = <&vencsys CLK_VENC_JPGENC>; > > + clock-names = "jpgenc"; > > + power-domains = <&spm > > MT8195_POWER_DOMAIN_VENC>; > > + }; > > + > > + jpgenc@1b030000 { > > + compatible = "mediatek,mt8195-jpgenc-hw"; > > + reg = <0 0x1b030000 0 0x10000>; > > + hw_id = <1>; > > + iommus = <&iommu_vpp > > M4U_PORT_L20_JPGENC_Y_RDMA>, > > + <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>, > > + <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>, > > + <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>; > > + interrupts = <GIC_SPI 347 > > IRQ_TYPE_LEVEL_HIGH 0>; > > + clocks = <&vencsys_core1 > > CLK_VENC_CORE1_JPGENC>; > > + clock-names = "jpgenc"; > > + power-domains = <&spm > > MT8195_POWER_DOMAIN_VENC_CORE1>; > > + }; > > + }; > > + }; > > -- > > 2.18.0 > > > >
On Mon, Jun 20, 2022 at 02:04:38PM +0800, kyrie.wu wrote: > On Fri, 2022-06-17 at 17:11 -0600, Rob Herring wrote: > > On Tue, Jun 14, 2022 at 08:10:18PM +0800, Irui Wang wrote: > > > From: kyrie wu <kyrie.wu@mediatek.com> > > > > > > Add mediatek,mt8195-jpgenc compatible to binding document. > > > > > > Signed-off-by: kyrie wu <kyrie.wu@mediatek.com> > > > --- > > > .../media/mediatek,mt8195-jpegenc.yaml | 153 > > > ++++++++++++++++++ > > > 1 file changed, 153 insertions(+) > > > create mode 100644 > > > Documentation/devicetree/bindings/media/mediatek,mt8195- > > > jpegenc.yaml > > > > > > diff --git > > > a/Documentation/devicetree/bindings/media/mediatek,mt8195- > > > jpegenc.yaml > > > b/Documentation/devicetree/bindings/media/mediatek,mt8195- > > > jpegenc.yaml > > > new file mode 100644 > > > index 000000000000..a7f9f723d5db > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/media/mediatek,mt8195- > > > jpegenc.yaml > > > @@ -0,0 +1,153 @@ > > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > > +%YAML 1.2 > > > +--- > > > +$id: > > > http://devicetree.org/schemas/media/mediatek,mt8195-jpegenc.yaml# > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > + > > > +title: MediaTek JPEG Encoder Device Tree Bindings > > > + > > > +maintainers: > > > + - kyrie wu <kyrie.wu@mediatek.corp-partner.google.com> > > > + > > > +description: |- > > > + MediaTek JPEG Encoder is the JPEG encode hardware present in > > > MediaTek SoCs > > > + > > > +properties: > > > + compatible: > > > + items: > > > + - const: mediatek,mt8195-jpgenc > > > + > > > + mediatek,jpegenc-multi-core: > > > + type: boolean > > > + description: | > > > + Indicates whether the jpeg encoder has multiple cores or > > > not. > > > + > > > + power-domains: > > > + maxItems: 1 > > > + > > > + iommus: > > > + maxItems: 4 > > > + description: | > > > + Points to the respective IOMMU block with master port as > > > argument, see > > > + Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml > > > for details. > > > + Ports are according to the HW. > > > + > > > + "#address-cells": > > > + const: 2 > > > + > > > + "#size-cells": > > > + const: 2 > > > + > > > + ranges: true > > > + > > > +# Required child node: > > > +patternProperties: > > > + "^jpgenc@[0-9a-f]+$": > > > + type: object > > > + description: | > > > + The jpeg encoder hardware device node which should be added > > > as subnodes to > > > + the main jpeg node. > > > + > > > + properties: > > > + compatible: > > > + const: mediatek,mt8195-jpgenc-hw > > > + > > > + reg: > > > + maxItems: 1 > > > + > > > + hw_id: > > > + description: | > > > + Current jpegenc hw id. > > > > Same question here. Surely, I asked sometime in the last 8 versions, > > but > > no explanation here and I'm not going to go look for it. > Dear Rob, > I'm sorry for not giving an accurate explanation in time. > The MT8195 has own two encoding hardwares, we use hw_id to > represent them. > hw_id = 0, for hardware 0, and hw_id = 1, repesents another one. > I will improve the description in the next version. Why do you care which one is which? We generally don't do instance indices in DT, so figure out how not to need this. Rob
On Tue, 2022-06-28 at 15:07 -0600, Rob Herring wrote: > On Mon, Jun 20, 2022 at 02:04:38PM +0800, kyrie.wu wrote: > > On Fri, 2022-06-17 at 17:11 -0600, Rob Herring wrote: > > > On Tue, Jun 14, 2022 at 08:10:18PM +0800, Irui Wang wrote: > > > > From: kyrie wu <kyrie.wu@mediatek.com> > > > > > > > > Add mediatek,mt8195-jpgenc compatible to binding document. > > > > > > > > Signed-off-by: kyrie wu <kyrie.wu@mediatek.com> > > > > --- > > > > .../media/mediatek,mt8195-jpegenc.yaml | 153 > > > > ++++++++++++++++++ > > > > 1 file changed, 153 insertions(+) > > > > create mode 100644 > > > > Documentation/devicetree/bindings/media/mediatek,mt8195- > > > > jpegenc.yaml > > > > > > > > diff --git > > > > a/Documentation/devicetree/bindings/media/mediatek,mt8195- > > > > jpegenc.yaml > > > > b/Documentation/devicetree/bindings/media/mediatek,mt8195- > > > > jpegenc.yaml > > > > new file mode 100644 > > > > index 000000000000..a7f9f723d5db > > > > --- /dev/null > > > > +++ b/Documentation/devicetree/bindings/media/mediatek,mt8195- > > > > jpegenc.yaml > > > > @@ -0,0 +1,153 @@ > > > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > > > +%YAML 1.2 > > > > +--- > > > > +$id: > > > > http://devicetree.org/schemas/media/mediatek,mt8195-jpegenc.yaml# > > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > > + > > > > +title: MediaTek JPEG Encoder Device Tree Bindings > > > > + > > > > +maintainers: > > > > + - kyrie wu <kyrie.wu@mediatek.corp-partner.google.com> > > > > + > > > > +description: |- > > > > + MediaTek JPEG Encoder is the JPEG encode hardware present in > > > > MediaTek SoCs > > > > + > > > > +properties: > > > > + compatible: > > > > + items: > > > > + - const: mediatek,mt8195-jpgenc > > > > + > > > > + mediatek,jpegenc-multi-core: > > > > + type: boolean > > > > + description: | > > > > + Indicates whether the jpeg encoder has multiple cores or > > > > not. > > > > + > > > > + power-domains: > > > > + maxItems: 1 > > > > + > > > > + iommus: > > > > + maxItems: 4 > > > > + description: | > > > > + Points to the respective IOMMU block with master port as > > > > argument, see > > > > + Documentation/devicetree/bindings/iommu/mediatek,iommu.y > > > > aml > > > > for details. > > > > + Ports are according to the HW. > > > > + > > > > + "#address-cells": > > > > + const: 2 > > > > + > > > > + "#size-cells": > > > > + const: 2 > > > > + > > > > + ranges: true > > > > + > > > > +# Required child node: > > > > +patternProperties: > > > > + "^jpgenc@[0-9a-f]+$": > > > > + type: object > > > > + description: | > > > > + The jpeg encoder hardware device node which should be > > > > added > > > > as subnodes to > > > > + the main jpeg node. > > > > + > > > > + properties: > > > > + compatible: > > > > + const: mediatek,mt8195-jpgenc-hw > > > > + > > > > + reg: > > > > + maxItems: 1 > > > > + > > > > + hw_id: > > > > + description: | > > > > + Current jpegenc hw id. > > > > > > Same question here. Surely, I asked sometime in the last 8 > > > versions, > > > but > > > no explanation here and I'm not going to go look for it. > > > > Dear Rob, > > I'm sorry for not giving an accurate explanation in time. > > The MT8195 has own two encoding hardwares, we use hw_id to > > represent them. > > hw_id = 0, for hardware 0, and hw_id = 1, repesents another one. > > I will improve the description in the next version. > > Why do you care which one is which? > > We generally don't do instance indices in DT, so figure out how not > to > need this. > > Rob Hi Bob, Thanks for your guidance, I will fix this issue in the next version. Kyrie.
diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegenc.yaml b/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegenc.yaml new file mode 100644 index 000000000000..a7f9f723d5db --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegenc.yaml @@ -0,0 +1,153 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek,mt8195-jpegenc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek JPEG Encoder Device Tree Bindings + +maintainers: + - kyrie wu <kyrie.wu@mediatek.corp-partner.google.com> + +description: |- + MediaTek JPEG Encoder is the JPEG encode hardware present in MediaTek SoCs + +properties: + compatible: + items: + - const: mediatek,mt8195-jpgenc + + mediatek,jpegenc-multi-core: + type: boolean + description: | + Indicates whether the jpeg encoder has multiple cores or not. + + power-domains: + maxItems: 1 + + iommus: + maxItems: 4 + description: | + Points to the respective IOMMU block with master port as argument, see + Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details. + Ports are according to the HW. + + "#address-cells": + const: 2 + + "#size-cells": + const: 2 + + ranges: true + +# Required child node: +patternProperties: + "^jpgenc@[0-9a-f]+$": + type: object + description: | + The jpeg encoder hardware device node which should be added as subnodes to + the main jpeg node. + + properties: + compatible: + const: mediatek,mt8195-jpgenc-hw + + reg: + maxItems: 1 + + hw_id: + description: | + Current jpegenc hw id. + + iommus: + minItems: 1 + maxItems: 32 + description: | + List of the hardware port in respective IOMMU block for current Socs. + Refer to bindings/iommu/mediatek,iommu.yaml. + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: jpgenc + + power-domains: + maxItems: 1 + + required: + - compatible + - reg + - hw_id + - iommus + - interrupts + - clocks + - clock-names + - power-domains + + additionalProperties: false + +required: + - compatible + - power-domains + - iommus + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/memory/mt8195-memory-port.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/clock/mt8195-clk.h> + #include <dt-bindings/power/mt8195-power.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + jpgenc_master { + compatible = "mediatek,mt8195-jpgenc"; + mediatek,jpegenc-multi-core; + power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; + iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>, + <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>, + <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>, + <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + jpgenc@1a030000 { + compatible = "mediatek,mt8195-jpgenc-hw"; + reg = <0 0x1a030000 0 0x10000>; + hw_id = <0>; + iommus = <&iommu_vdo M4U_PORT_L19_JPGENC_Y_RDMA>, + <&iommu_vdo M4U_PORT_L19_JPGENC_C_RDMA>, + <&iommu_vdo M4U_PORT_L19_JPGENC_Q_TABLE>, + <&iommu_vdo M4U_PORT_L19_JPGENC_BSDMA>; + interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&vencsys CLK_VENC_JPGENC>; + clock-names = "jpgenc"; + power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; + }; + + jpgenc@1b030000 { + compatible = "mediatek,mt8195-jpgenc-hw"; + reg = <0 0x1b030000 0 0x10000>; + hw_id = <1>; + iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>, + <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>, + <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>, + <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>; + interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGENC>; + clock-names = "jpgenc"; + power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; + }; + }; + };