| Message ID | 20220728071637.22364-3-peter.wang@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | ufs: allow vendor disable wb toggle in clock scaling | expand |
On Thu, 2022-07-28 at 15:16 +0800, peter.wang@mediatek.com wrote: > From: Peter Wang <peter.wang@mediatek.com> > > Set UFSHCD_CAP_WB_WITH_CLK_SCALING for qcom to compatible legacy > design. > > Signed-off-by: Peter Wang <peter.wang@mediatek.com> > --- > drivers/ufs/host/ufs-qcom.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs- > qcom.c > index f10d4668814c..f8c9a78e7776 100644 > --- a/drivers/ufs/host/ufs-qcom.c > +++ b/drivers/ufs/host/ufs-qcom.c > @@ -869,7 +869,7 @@ static void ufs_qcom_set_caps(struct ufs_hba > *hba) > struct ufs_qcom_host *host = ufshcd_get_variant(hba); > > hba->caps |= UFSHCD_CAP_CLK_GATING | > UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; > - hba->caps |= UFSHCD_CAP_CLK_SCALING; > + hba->caps |= UFSHCD_CAP_CLK_SCALING | > UFSHCD_CAP_WB_WITH_CLK_SCALING; > hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND; > hba->caps |= UFSHCD_CAP_WB_EN; > hba->caps |= UFSHCD_CAP_CRYPTO; Hi peter, If WB is on/off based on clk scaling up/down is legacy design, maybe you have a more advanced design. It is true there is an issue since we didn't differentiate the read or write. WB is only for write. How to know this time clk scaling is for write from driver level, not possible now. Kind regards, Bean
On 7/29/22 5:57 AM, Bean Huo wrote: > On Thu, 2022-07-28 at 15:16 +0800, peter.wang@mediatek.com wrote: >> From: Peter Wang <peter.wang@mediatek.com> >> >> Set UFSHCD_CAP_WB_WITH_CLK_SCALING for qcom to compatible legacy >> design. >> >> Signed-off-by: Peter Wang <peter.wang@mediatek.com> >> --- >> drivers/ufs/host/ufs-qcom.c | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs- >> qcom.c >> index f10d4668814c..f8c9a78e7776 100644 >> --- a/drivers/ufs/host/ufs-qcom.c >> +++ b/drivers/ufs/host/ufs-qcom.c >> @@ -869,7 +869,7 @@ static void ufs_qcom_set_caps(struct ufs_hba >> *hba) >> struct ufs_qcom_host *host = ufshcd_get_variant(hba); >> >> hba->caps |= UFSHCD_CAP_CLK_GATING | >> UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; >> - hba->caps |= UFSHCD_CAP_CLK_SCALING; >> + hba->caps |= UFSHCD_CAP_CLK_SCALING | >> UFSHCD_CAP_WB_WITH_CLK_SCALING; >> hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND; >> hba->caps |= UFSHCD_CAP_WB_EN; >> hba->caps |= UFSHCD_CAP_CRYPTO; > Hi peter, > > If WB is on/off based on clk scaling up/down is legacy design, maybe > you have a more advanced design. It is true there is an issue since we > didn't differentiate the read or write. WB is only for write. How to > know this time clk scaling is for write from driver level, not possible > now. > > Kind regards, > Bean Hi Bean, Yes, we don't know if clock scaling up/down is for write or read. But we want to keep WB always on even clock scaling down. This is why we need this patch, let different host can choose toggle wb or not. Thanks. Peter
diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index f10d4668814c..f8c9a78e7776 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -869,7 +869,7 @@ static void ufs_qcom_set_caps(struct ufs_hba *hba) struct ufs_qcom_host *host = ufshcd_get_variant(hba); hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; - hba->caps |= UFSHCD_CAP_CLK_SCALING; + hba->caps |= UFSHCD_CAP_CLK_SCALING | UFSHCD_CAP_WB_WITH_CLK_SCALING; hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND; hba->caps |= UFSHCD_CAP_WB_EN; hba->caps |= UFSHCD_CAP_CRYPTO;