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[194.187.74.233]) by smtp.gmail.com with ESMTPSA id 1-20020a170906218100b008720c458bd4sm9509608eju.3.2023.01.31.22.52.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 22:52:30 -0800 (PST) From: =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= To: Srinivas Kandagatla , Rob Herring , Krzysztof Kozlowski Cc: Matthias Brugger , Kunihiko Hayashi , Masami Hiramatsu , linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= Subject: [PATCH 2/4] nvmem: add generic driver for devices with MMIO access Date: Wed, 1 Feb 2023 07:47:15 +0100 Message-Id: <20230201064717.18410-3-zajec5@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230201064717.18410-1-zajec5@gmail.com> References: <20230201064717.18410-1-zajec5@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230131_225234_371278_CFC65D75 X-CRM114-Status: GOOD ( 24.22 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org From: Rafał Miłecki With nvmem layouts in place we should now work on plain content access NVMEM drivers (e.g. MMIO one). Actual NVMEM content handling should go to layout drivers. Signed-off-by: Rafał Miłecki --- drivers/nvmem/Kconfig | 10 ++++++ drivers/nvmem/Makefile | 2 ++ drivers/nvmem/mmio.c | 80 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 92 insertions(+) create mode 100644 drivers/nvmem/mmio.c diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig index 789729ff7e50..9eb5e93f0455 100644 --- a/drivers/nvmem/Kconfig +++ b/drivers/nvmem/Kconfig @@ -170,6 +170,16 @@ config NVMEM_MICROCHIP_OTPC This driver enable the OTP controller available on Microchip SAMA7G5 SoCs. It controls the access to the OTP memory connected to it. +config NVMEM_MMIO + tristate "MMIO access based NVMEM support" + depends on HAS_IOMEM + help + This driver provides support for NVMEM devices that can be accessed + using MMIO. + + This driver can also be built as a module. If so, the module + will be called nvmem-mmio. + config NVMEM_MTK_EFUSE tristate "Mediatek SoCs EFUSE support" depends on ARCH_MEDIATEK || COMPILE_TEST diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile index 442f9a4876a5..2f2bed7cdf24 100644 --- a/drivers/nvmem/Makefile +++ b/drivers/nvmem/Makefile @@ -36,6 +36,8 @@ obj-$(CONFIG_NVMEM_MESON_MX_EFUSE) += nvmem_meson_mx_efuse.o nvmem_meson_mx_efuse-y := meson-mx-efuse.o obj-$(CONFIG_NVMEM_MICROCHIP_OTPC) += nvmem-microchip-otpc.o nvmem-microchip-otpc-y := microchip-otpc.o +obj-$(CONFIG_NVMEM_MMIO) += nvmem-mmio.o +nvmem-mmio-y := mmio.o obj-$(CONFIG_NVMEM_MTK_EFUSE) += nvmem_mtk-efuse.o nvmem_mtk-efuse-y := mtk-efuse.o obj-$(CONFIG_NVMEM_MXS_OCOTP) += nvmem-mxs-ocotp.o diff --git a/drivers/nvmem/mmio.c b/drivers/nvmem/mmio.c new file mode 100644 index 000000000000..19c8880dc675 --- /dev/null +++ b/drivers/nvmem/mmio.c @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023 Rafał Miłecki + */ + +#include +#include +#include +#include +#include +#include +#include + +struct mmio_nvmem { + void __iomem *base; +}; + +static int mmio_nvmem_read(void *context, unsigned int offset, void *val, size_t bytes) +{ + struct mmio_nvmem *priv = context; + + memcpy_fromio(val, priv->base, bytes); + + return 0; +} + +static int mmio_nvmem_probe(struct platform_device *pdev) +{ + struct nvmem_config config = { + .name = "mmio-nvmem", + .read_only = true, + .reg_read = mmio_nvmem_read, + }; + struct device *dev = &pdev->dev; + struct mmio_nvmem *priv; + struct resource *res; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + config.dev = dev; + config.size = resource_size(res); + config.word_size = sizeof(u8); + config.stride = sizeof(u8); + config.priv = priv; + + if (!device_property_present(dev, "read-only")) + dev_warn(dev, "Writing is not supported yet"); + + return PTR_ERR_OR_ZERO(devm_nvmem_register(dev, &config)); +} + +static const struct of_device_id mmio_nvmem_of_match_table[] = { + { .compatible = "mmio-nvmem", }, + {}, +}; + +static struct platform_driver mmio_nvmem_driver = { + .probe = mmio_nvmem_probe, + .driver = { + .name = "mmio_nvmem", + .of_match_table = mmio_nvmem_of_match_table, + }, +}; + +static int __init mmio_nvmem_init(void) +{ + return platform_driver_register(&mmio_nvmem_driver); +} + +subsys_initcall_sync(mmio_nvmem_init); + +MODULE_AUTHOR("Rafał Miłecki"); +MODULE_LICENSE("GPL"); +MODULE_DEVICE_TABLE(of, mmio_nvmem_of_match_table);