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[93.5.22.158]) by smtp.googlemail.com with ESMTPSA id 25-20020a05600c025900b003ed2c0a0f37sm17601988wmj.35.2023.04.26.03.49.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Apr 2023 03:49:46 -0700 (PDT) From: Alexandre Mergnat Date: Wed, 26 Apr 2023 12:49:09 +0200 Subject: [PATCH v6 09/12] arm64: dts: mediatek: add ethernet support for mt8365-evk MIME-Version: 1.0 Message-Id: <20230203-evk-board-support-v6-9-8d6b1cfe7f29@baylibre.com> References: <20230203-evk-board-support-v6-0-8d6b1cfe7f29@baylibre.com> In-Reply-To: <20230203-evk-board-support-v6-0-8d6b1cfe7f29@baylibre.com> To: Catalin Marinas , Will Deacon , Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , AngeloGioacchino Del Regno Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, Alexandre Mergnat , Kevin Hilman X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2481; i=amergnat@baylibre.com; h=from:subject:message-id; bh=7EszwhdlVZWdtXiG7X73axwD3s6F8ryAMeolNiULVRc=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBkSQG/HPyHY0PZGh5cXqQyVV4RE1tHH+CJa2pwV4Gu BKP6bTmJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCZEkBvwAKCRArRkmdfjHURf4FD/ 42hXlvJEcBqPTrWTYquuNtcQ0VEdhVDQvrMXohmXxJ+pnOfoBhJ/1kg5U4F/S/D2LlHFhsLx1d0P1j n+JLdlh80wm5uWNbKpoS30ygPLCUupERN8Zn0snU9KeXNuCn9ZDT4PjLMLEiHQPjNyzQKHaTqLEaH1 idSIpMKQywQW6X3PIxhYFP/soKH1L53bYKjre0vjeuROfMLatYXd5xF/gxDj1CNkn4ked+uBbBVOxO 1tRbwofJhQA1Mr4UR/dM8sTItLhVSTTASS7DtSXb/1WJZxYoNxyBxvLJsK/yuUlU4MCLnwPBm8OwCL YvyWio/+DH9gwNTthh5Gp7Jjzer3D4wmvUflj/AyY3ut0dGOnU5nvxCe1iABi4oleIqiQqa6VM6zYr aIwE3GFf8tdlz+jB44N04jgqxGpoZyn/cxQHwwuke85qb6/RNGDcjjOKvGy9WIeenn1pwCdOIHNsw9 Qj6rC7+CHyoaREhLk4C76CKFOOnTwPRPIDILOcY0gZhKAPwqsoTl2pnYxewz0lUNMHBWMKSlPr5GlE HXFMydvj5igYx/VlYBFkiUfwn/XVApdfInmU1HRDgGSHMKHMLjbL9isTBVDNiU0+6rE5ECgqMAixCO vUzllLkYr6C4OBzC3Fn/9bJoqci3vs5XG4sKPgw9cvpOXjqk6Kbvjj3UsDWA== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230426_034949_652355_01148448 X-CRM114-Status: GOOD ( 11.85 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org - Enable "vibr" and "vsim2" regulators to power the ethernet chip. Tested-by: Kevin Hilman Signed-off-by: Alexandre Mergnat --- arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 57 +++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts index 913e09545030..5a4c41dbd3a5 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts @@ -88,6 +88,28 @@ optee_reserved: optee@43200000 { }; }; +ðernet { + pinctrl-0 = <ðernet_pins>; + pinctrl-names = "default"; + phy-handle = <ð_phy>; + phy-mode = "rmii"; + /* + * Ethernet and HDMI (DSI0) are sharing pins. + * Only one can be enabled at a time and require the physical switch + * SW2101 to be set on LAN position + */ + status = "disabled"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + eth_phy: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + &i2c0 { clock-frequency = <100000>; pinctrl-0 = <&i2c0_pins>; @@ -137,12 +159,47 @@ &mt6357_pmic { #interrupt-cells = <2>; }; +/* Needed by analog switch (multiplexer), HDMI and ethernet */ +&mt6357_vibr_reg { + regulator-always-on; +}; + /* Needed by MSDC IP */ &mt6357_vmc_reg { regulator-always-on; }; +/* Needed by ethernet */ +&mt6357_vsim2_reg { + regulator-always-on; +}; + &pio { + ethernet_pins: ethernet-pins { + phy_reset_pins { + pinmux = ; + }; + + rmii_pins { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + }; + gpio_keys: gpio-keys-pins { pins { pinmux = ;