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[93.5.22.158]) by smtp.googlemail.com with ESMTPSA id o12-20020adfe80c000000b002fe13ec49fasm5010587wrm.98.2023.05.26.06.10.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 May 2023 06:10:52 -0700 (PDT) From: Alexandre Mergnat Date: Fri, 26 May 2023 15:10:43 +0200 Subject: [PATCH v3] clk: mediatek: mt8365: Fix index issue MIME-Version: 1.0 Message-Id: <20230517-fix-clk-index-v3-1-be4df46065c4@baylibre.com> X-B4-Tracking: v=1; b=H4sIANKvcGQC/32Oy27CMBBFfwV5zRA/Ept21f9ALDxmQkZAEtmpB UL599rsWqksz5XO0X2KRJEpic/NU0TKnHgaC5jtRoTBj2cCPhUWWmojO+Wg5zuE6wV4PNEdPqx sDfredkiiOOgTAUY/hqFa33OT7a6FGFSzTDOH5rbsje2aX5UqzpHK9jpyOBYeOC1TfLx+ZVXX/ y5kBRJUq6VzXjmj8Qv948oYaRemm6ixrN8GdA2g3dtAfUBHfwLruv4AJQLa3ScBAAA= To: Michael Turquette , Stephen Boyd , Matthias Brugger , AngeloGioacchino Del Regno , Chen-Yu Tsai Cc: Conor Dooley , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Alexandre Mergnat X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4771; i=amergnat@baylibre.com; h=from:subject:message-id; bh=s9ktG6EMZDgpIOSQmeRBQyxInHPyLL6rYL7iN6uRfXE=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBkcK/coUhPBZM0NAJVX8FieOT3nCN+slKpZTWjfoPT pl/E0R6JAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCZHCv3AAKCRArRkmdfjHURZ0NEA CQX7CxAKFArV5C9+fkjK//dSNLEXu7FlKTnE+YdqaCObcffYXvZP6Ya2cvZOh2i+6p7gO5YnIBUjmu gUbV8GXpj81IuQX8stw6iFE3ZHiYaceE7E8QIs93lEsfOPaHDwZTA/eJQDKXQtMvSOQyS7YVn3UAZ0 htqQdx2RGy8i0UB05+ScCVD8hRjS2xj5F/C+NaH0X1qVvD8C7D7swzuCBHL0DKExqpTsVbnGJJlgtb Ul4nTyCrh1POLS09VxC0hy9bUxSO8yrFncZS3nHhvT80uDxYmb2tbQoKDRJsSsXKVBJWO+IlqW7AM5 ohPYMDBnZLBXRYcqTZraeRdDpnal0VVXME5KjFyc8b20CEvUzhMK0PxSdbWa8UZD+8inPJjA9Nod9b Zsq4beLUVzfeCLtOhzUU/yp61DqWgOcSEaMPpa0miDKV4pEFrAK+Uvuum+Jiolpqtw2ZqbpC9Af+// +yOoCKrGbnryoV5TBVrafsmUQ8LNTrH9ve/OU9CYAiHtq4OLID7K/CbTRCe4359KBRRt2zDw9KhOVt ED1zQCTOvhX2n2s1dcFTYRZgIPirkfdy9aBknnnG6n/3oXVSE6oB0XEdkg7ggSU0XDsNfmDYCN4cTm ZwuSzxTmVdIL7Oi8drYGx3G/AVrYyQ1mSDhQAp+R0D5fWKL+QNwUDkH6ewOQ== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230526_061057_321288_04A58085 X-CRM114-Status: GOOD ( 16.88 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Before the patch [1], the clock probe was done directly in the clk-mt8365 driver. In this probe function, the array which stores the data clocks is sized using the higher defined numbers (*_NR_CLOCK) in the clock lists [2]. Currently, with the patch [1], the specific clk-mt8365 probe function is replaced by the mtk generic one [3], which size the clock data array by adding all the clock descriptor array size provided by the clk-mt8365 driver. Actually, all clock indexes come from the header file [2], that mean, if there are more clock (then more index) in the header file [2] than the number of clock declared in the clock descriptor arrays (which is the case currently), the clock data array will be undersized and then the generic probe function will overflow when it will try to write in "clk_data[CLK_INDEX]". Actually, instead of crashing at boot, the probe function returns an error in the log which looks like: "of_clk_hw_onecell_get: invalid index 135", then this clock isn't enabled. Solve this issue by adding in the driver the missing clocks declared in the header clock file [2]. [1]: Commit ffe91cb28f6a ("clk: mediatek: mt8365: Convert to mtk_clk_simple_{probe,remove}()") [2]: include/dt-bindings/clock/mediatek,mt8365-clk.h [3]: drivers/clk/mediatek/clk-mtk.c Fixes: ffe91cb28f6a ("clk: mediatek: mt8365: Convert to mtk_clk_simple_{probe,remove}()") Signed-off-by: Alexandre Mergnat Reviewed-by: Markus Schneider-Pargmann Tested-by: Markus Schneider-Pargmann --- Fix a regression which prevent the initialization of the latest indexed clocks. The regression is introduced with [1]. [1]: Commit ffe91cb28f6a ("clk: mediatek: mt8365: Convert to mtk_clk_simple_{probe,remove}()") --- Changes in v3: - Remove all binding changes. - Link to v2: https://lore.kernel.org/r/20230517-fix-clk-index-v2-0-1b686cefcb7e@baylibre.com Changes in v2: - Add the missing clocks in the mt8365 clock driver. - Revert all change in binding file except for one clock. - Link to v1: https://lore.kernel.org/r/20230517-fix-clk-index-v1-0-142077a1732b@baylibre.com --- drivers/clk/mediatek/clk-mt8365.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) --- base-commit: ac9a78681b921877518763ba0e89202254349d1b change-id: 20230517-fix-clk-index-96043baf65be Best regards, diff --git a/drivers/clk/mediatek/clk-mt8365.c b/drivers/clk/mediatek/clk-mt8365.c index 6b4e193f648d..c366ac1611e6 100644 --- a/drivers/clk/mediatek/clk-mt8365.c +++ b/drivers/clk/mediatek/clk-mt8365.c @@ -23,6 +23,7 @@ static DEFINE_SPINLOCK(mt8365_clk_lock); static const struct mtk_fixed_clk top_fixed_clks[] = { + FIXED_CLK(CLK_TOP_CLK_NULL, "clk_null", NULL, 0), FIXED_CLK(CLK_TOP_I2S0_BCK, "i2s0_bck", NULL, 26000000), FIXED_CLK(CLK_TOP_DSI0_LNTC_DSICK, "dsi0_lntc_dsick", "clk26m", 75000000), @@ -559,6 +560,14 @@ static const struct mtk_clk_divider top_adj_divs[] = { 0x324, 16, 8, CLK_DIVIDER_ROUND_CLOSEST), DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV3, "apll12_ck_div3", "apll_i2s3_sel", 0x324, 24, 8, CLK_DIVIDER_ROUND_CLOSEST), + DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV4, "apll12_ck_div4", "apll_tdmout_sel", + 0x328, 0, 8, CLK_DIVIDER_ROUND_CLOSEST), + DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV4B, "apll12_ck_div4b", "apll_tdmout_sel", + 0x328, 8, 8, CLK_DIVIDER_ROUND_CLOSEST), + DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV5, "apll12_ck_div5", "apll_tdmin_sel", + 0x328, 16, 8, CLK_DIVIDER_ROUND_CLOSEST), + DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV5B, "apll12_ck_div5b", "apll_tdmin_sel", + 0x328, 24, 8, CLK_DIVIDER_ROUND_CLOSEST), DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV6, "apll12_ck_div6", "apll_spdif_sel", 0x32c, 0, 8, CLK_DIVIDER_ROUND_CLOSEST), }; @@ -696,6 +705,7 @@ static const struct mtk_gate ifr_clks[] = { GATE_IFR3(CLK_IFR_GCPU, "ifr_gcpu", "axi_sel", 8), GATE_IFR3(CLK_IFR_TRNG, "ifr_trng", "axi_sel", 9), GATE_IFR3(CLK_IFR_AUXADC, "ifr_auxadc", "clk26m", 10), + GATE_IFR3(CLK_IFR_CPUM, "ifr_cpum", "clk26m", 11), GATE_IFR3(CLK_IFR_AUXADC_MD, "ifr_auxadc_md", "clk26m", 14), GATE_IFR3(CLK_IFR_AP_DMA, "ifr_ap_dma", "axi_sel", 18), GATE_IFR3(CLK_IFR_DEBUGSYS, "ifr_debugsys", "axi_sel", 24), @@ -717,6 +727,8 @@ static const struct mtk_gate ifr_clks[] = { GATE_IFR5(CLK_IFR_PWRAP_TMR, "ifr_pwrap_tmr", "clk26m", 12), GATE_IFR5(CLK_IFR_PWRAP_SPI, "ifr_pwrap_spi", "clk26m", 13), GATE_IFR5(CLK_IFR_PWRAP_SYS, "ifr_pwrap_sys", "clk26m", 14), + GATE_MTK_FLAGS(CLK_IFR_MCU_PM_BK, "ifr_mcu_pm_bk", NULL, &ifr5_cg_regs, + 17, &mtk_clk_gate_ops_setclr, CLK_IGNORE_UNUSED), GATE_IFR5(CLK_IFR_IRRX_26M, "ifr_irrx_26m", "clk26m", 22), GATE_IFR5(CLK_IFR_IRRX_32K, "ifr_irrx_32k", "clk32k", 23), GATE_IFR5(CLK_IFR_I2C0_AXI, "ifr_i2c0_axi", "i2c_sel", 24),