| Message ID | 20230630100321.1951138-2-jstephan@baylibre.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add Mediatek ISP3.0 | expand |
On Fri, 30 Jun 2023 12:01:50 +0200, Julien Stephan wrote: > From: Louis Kuo <louis.kuo@mediatek.com> > > This adds the bindings, for the mediatek ISP3.0 SENINF module embedded in > some Mediatek SoC, such as the mt8365 > > Signed-off-by: Louis Kuo <louis.kuo@mediatek.com> > Signed-off-by: Phi-Bang Nguyen <pnguyen@baylibre.com> > Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > Signed-off-by: Julien Stephan <jstephan@baylibre.com> > --- > .../media/mediatek,mt8365-seninf.yaml | 295 ++++++++++++++++++ > MAINTAINERS | 7 + > 2 files changed, 302 insertions(+) > create mode 100644 Documentation/devicetree/bindings/media/mediatek,mt8365-seninf.yaml > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: Documentation/devicetree/bindings/media/mediatek,mt8365-seninf.example.dts:28:18: fatal error: dt-bindings/power/mediatek,mt8365-power.h: No such file or directory 28 | #include <dt-bindings/power/mediatek,mt8365-power.h> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ compilation terminated. make[1]: *** [scripts/Makefile.lib:419: Documentation/devicetree/bindings/media/mediatek,mt8365-seninf.example.dtb] Error 1 make[1]: *** Waiting for unfinished jobs.... make: *** [Makefile:1512: dt_binding_check] Error 2 doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20230630100321.1951138-2-jstephan@baylibre.com The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.
On Fri, Jun 30, 2023 at 12:01:50PM +0200, Julien Stephan wrote: > From: Louis Kuo <louis.kuo@mediatek.com> > > This adds the bindings, for the mediatek ISP3.0 SENINF module embedded in > some Mediatek SoC, such as the mt8365 > > Signed-off-by: Louis Kuo <louis.kuo@mediatek.com> > Signed-off-by: Phi-Bang Nguyen <pnguyen@baylibre.com> > Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > Signed-off-by: Julien Stephan <jstephan@baylibre.com> > --- > .../media/mediatek,mt8365-seninf.yaml | 295 ++++++++++++++++++ > MAINTAINERS | 7 + > 2 files changed, 302 insertions(+) > create mode 100644 Documentation/devicetree/bindings/media/mediatek,mt8365-seninf.yaml > > diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8365-seninf.yaml b/Documentation/devicetree/bindings/media/mediatek,mt8365-seninf.yaml > new file mode 100644 > index 000000000000..1697e94853f5 > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/mediatek,mt8365-seninf.yaml > @@ -0,0 +1,295 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +# Copyright (c) 2023 MediaTek, BayLibre > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/media/mediatek,mt8365-seninf.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek Sensor Interface 3.0 > + > +maintainers: > + - Laurent Pinchart <laurent.pinchart@ideasonboard.com> > + - Julien Stephan <jstephan@baylibre.com> > + - Andy Hsieh <andy.hsieh@mediatek.com> > + > +description: > + The ISP3.0 SENINF is the CSI-2 and parallel camera sensor interface found in > + multiple MediaTek SoCs. It can support up to three physical CSI-2 > + input ports, configured in DPHY (2 or 4 data lanes) or CPHY depending on the SoC. > + On the output side, SENINF can be connected either to CAMSV instance or > + to the internal ISP. CAMSV is used to transfer the sensor data (Raw, YUV) > + to DRAM directly, without internal ISP processing. > + > +properties: > + compatible: > + const: mediatek,mt8365-seninf > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + power-domains: > + maxItems: 1 > + > + clocks: > + items: > + - description: Seninf camsys clock > + - description: Seninf top mux clock > + > + clock-names: > + items: > + - const: camsys > + - const: top_mux > + > + phys: > + minItems: 1 > + maxItems: 4 > + description: > + phandle to the PHYs connected to CSI0/A, CSI1, CSI2 and CSI0B > + > + phy-names: > + minItems: 1 > + items: > + - const: csi0 > + - const: csi1 > + - const: csi2 > + - const: csi0b > + > + ports: > + $ref: /schemas/graph.yaml#/properties/ports > + > + properties: > + port@0: > + $ref: /schemas/graph.yaml#/$defs/port-base > + unevaluatedProperties: false > + description: CSI0 or CSI0A port > + > + properties: > + endpoint: > + $ref: video-interfaces.yaml# > + unevaluatedProperties: false > + > + properties: > + clock-lanes: > + maxItems: 1 > + data-lanes: > + minItems: 1 > + maxItems: 4 > + > + port@1: > + $ref: /schemas/graph.yaml#/$defs/port-base > + unevaluatedProperties: false > + description: CSI1 port > + > + properties: > + endpoint: > + $ref: video-interfaces.yaml# > + unevaluatedProperties: false > + > + properties: > + clock-lanes: > + maxItems: 1 > + data-lanes: > + minItems: 1 > + maxItems: 4 > + > + port@2: > + $ref: /schemas/graph.yaml#/$defs/port-base > + unevaluatedProperties: false > + description: CSI2 port > + > + properties: > + endpoint: > + $ref: video-interfaces.yaml# > + unevaluatedProperties: false > + > + properties: > + clock-lanes: > + maxItems: 1 > + data-lanes: > + minItems: 1 > + maxItems: 4 > + > + port@3: > + $ref: /schemas/graph.yaml#/$defs/port-base > + unevaluatedProperties: false > + description: CSI0B port > + > + properties: > + endpoint: > + $ref: video-interfaces.yaml# > + unevaluatedProperties: false > + > + properties: > + clock-lanes: > + maxItems: 1 > + data-lanes: > + minItems: 1 > + maxItems: 2 > + > + port@4: > + $ref: /schemas/graph.yaml#/$defs/port-base /schemas/graph.yaml#/properties/port > + unevaluatedProperties: false Drop > + description: connection point for cam0 > + > + properties: Drop all this. Don't need to define endpoint as /schemas/graph.yaml#/properties/port already does. Same on other ports. > + endpoint: > + $ref: /schemas/graph.yaml#/$defs/endpoint-base > + unevaluatedProperties: false
diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8365-seninf.yaml b/Documentation/devicetree/bindings/media/mediatek,mt8365-seninf.yaml new file mode 100644 index 000000000000..1697e94853f5 --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mt8365-seninf.yaml @@ -0,0 +1,295 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (c) 2023 MediaTek, BayLibre +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek,mt8365-seninf.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Sensor Interface 3.0 + +maintainers: + - Laurent Pinchart <laurent.pinchart@ideasonboard.com> + - Julien Stephan <jstephan@baylibre.com> + - Andy Hsieh <andy.hsieh@mediatek.com> + +description: + The ISP3.0 SENINF is the CSI-2 and parallel camera sensor interface found in + multiple MediaTek SoCs. It can support up to three physical CSI-2 + input ports, configured in DPHY (2 or 4 data lanes) or CPHY depending on the SoC. + On the output side, SENINF can be connected either to CAMSV instance or + to the internal ISP. CAMSV is used to transfer the sensor data (Raw, YUV) + to DRAM directly, without internal ISP processing. + +properties: + compatible: + const: mediatek,mt8365-seninf + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + power-domains: + maxItems: 1 + + clocks: + items: + - description: Seninf camsys clock + - description: Seninf top mux clock + + clock-names: + items: + - const: camsys + - const: top_mux + + phys: + minItems: 1 + maxItems: 4 + description: + phandle to the PHYs connected to CSI0/A, CSI1, CSI2 and CSI0B + + phy-names: + minItems: 1 + items: + - const: csi0 + - const: csi1 + - const: csi2 + - const: csi0b + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: CSI0 or CSI0A port + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + data-lanes: + minItems: 1 + maxItems: 4 + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: CSI1 port + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + data-lanes: + minItems: 1 + maxItems: 4 + + port@2: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: CSI2 port + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + data-lanes: + minItems: 1 + maxItems: 4 + + port@3: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: CSI0B port + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + data-lanes: + minItems: 1 + maxItems: 2 + + port@4: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: connection point for cam0 + + properties: + endpoint: + $ref: /schemas/graph.yaml#/$defs/endpoint-base + unevaluatedProperties: false + + port@5: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: connection point for cam1 + + properties: + endpoint: + $ref: /schemas/graph.yaml#/$defs/endpoint-base + unevaluatedProperties: false + + port@6: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: connection point for camsv0 + + properties: + endpoint: + $ref: /schemas/graph.yaml#/$defs/endpoint-base + unevaluatedProperties: false + + port@7: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: connection point for camsv1 + + properties: + endpoint: + $ref: /schemas/graph.yaml#/$defs/endpoint-base + unevaluatedProperties: false + + port@8: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: connection point for camsv2 + + properties: + endpoint: + $ref: /schemas/graph.yaml#/$defs/endpoint-base + unevaluatedProperties: false + + port@9: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: connection point for camsv3 + + properties: + endpoint: + $ref: /schemas/graph.yaml#/$defs/endpoint-base + unevaluatedProperties: false + + required: + - port@0 + - port@1 + - port@2 + - port@3 + - port@4 + - port@5 + - port@6 + - port@7 + - port@8 + - port@9 + +required: + - compatible + - interrupts + - clocks + - clock-names + - power-domains + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/mediatek,mt8365-clk.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/phy/phy.h> + #include <dt-bindings/power/mediatek,mt8365-power.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + seninf: seninf@15040000 { + compatible = "mediatek,mt8365-seninf"; + reg = <0 0x15040000 0 0x6000>; + interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_LOW>; + clocks = <&camsys CLK_CAM_SENIF>, + <&topckgen CLK_TOP_SENIF_SEL>; + clock-names = "camsys", "top_mux"; + + power-domains = <&spm MT8365_POWER_DOMAIN_CAM>; + + phys = <&mipi_csi0 PHY_TYPE_DPHY>; + phy-names = "csi0"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + seninf_in1: endpoint { + clock-lanes = <2>; + data-lanes = <1 3 0 4>; + remote-endpoint = <&isp1_out>; + }; + }; + + port@1 { + reg = <1>; + }; + + port@2 { + reg = <2>; + }; + + port@3 { + reg = <3>; + }; + + port@4 { + reg = <4>; + seninf_camsv1_endpoint: endpoint { + remote-endpoint = <&camsv1_endpoint>; + }; + }; + + port@5 { + reg = <5>; + }; + + port@6 { + reg = <6>; + }; + + port@7 { + reg = <7>; + }; + + port@8 { + reg = <8>; + }; + + port@9 { + reg = <9>; + }; + + }; + }; + }; + +... diff --git a/MAINTAINERS b/MAINTAINERS index e0976ae2a523..af273a477139 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13350,6 +13350,13 @@ M: Sean Wang <sean.wang@mediatek.com> S: Maintained F: drivers/char/hw_random/mtk-rng.c +MEDIATEK ISP3.0 DRIVER +M: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +M: Julien Stephan <jstephan@baylibre.com> +M: Andy Hsieh <andy.hsieh@mediatek.com> +S: Supported +F: Documentation/devicetree/bindings/media/mediatek,mt8365-seninf.yaml + MEDIATEK SMI DRIVER M: Yong Wu <yong.wu@mediatek.com> L: linux-mediatek@lists.infradead.org (moderated for non-subscribers)