Message ID | 20230831130826.5592-4-peter.wang@mediatek.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | Fix abnormal clock scaling behaviors | expand |
diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c index 057549b0e586..d72fa2c1e316 100644 --- a/drivers/ufs/core/ufshcd.c +++ b/drivers/ufs/core/ufshcd.c @@ -1430,6 +1430,13 @@ static int ufshcd_devfreq_target(struct device *dev, return 0; } + /* Skip scaling clock when clock scaling is suspended */ + if (hba->clk_scaling.is_suspended) { + spin_unlock_irqrestore(hba->host->host_lock, irq_flags); + dev_warn(hba->dev, "clock scaling is suspended, skip"); + return 0; + } + if (!hba->clk_scaling.active_reqs) sched_clk_scaling_suspend_work = true;