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Wed, 20 Dec 2023 18:39:20 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 20 Dec 2023 18:39:20 +0800 From: William-tw Lin To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Srinivas Kandagatla CC: , , , , William-tw Lin Subject: [PATCH v3 1/3] arm64: dts: Add node for chip info driver Date: Wed, 20 Dec 2023 18:38:59 +0800 Message-ID: <20231220103901.22180-2-william-tw.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231220103901.22180-1-william-tw.lin@mediatek.com> References: <20231220103901.22180-1-william-tw.lin@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--4.895700-8.000000 X-TMASE-MatchedRID: jhJi18RLqAJbbwmb1mOeyx+WEMjoO9WWTJDl9FKHbrk3nZaS9VtZrqPF jJEFr+olwXCBO/GKkVr3FLeZXNZS4CiM3WUt6LtFNK4pZj/Hg0kjmtV8Q/0SEs6K5vv4EqP1JoX /CQCmyyMFoF08IxPyBtL3VNJRBhun0YfblHonBjiRVhCh489z1mkW5gEw17GTeZUpm6wun3ba/0 6NhYDa4wyzCDjlUx89djekYOaiKTo= X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--4.895700-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 98ED5DAA45140FF0638775DBDE6E76C16BC381C1F39C3431CDEDB8C1ECEBE6992000:8 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231220_024029_199725_B40E46E9 X-CRM114-Status: GOOD ( 10.95 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Add dts node for socinfo retrieval for the following projects: MT8173, MT8183, MT8186, MT8192, MT8195 Signed-off-by: William-tw Lin --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 9 +++++++++ arch/arm64/boot/dts/mediatek/mt8183.dtsi | 9 +++++++++ arch/arm64/boot/dts/mediatek/mt8186.dtsi | 4 ++++ arch/arm64/boot/dts/mediatek/mt8192.dtsi | 8 ++++++++ arch/arm64/boot/dts/mediatek/mt8195.dtsi | 3 +++ 5 files changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index c47d7d900f28..06916e60679a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -590,6 +590,15 @@ reg = <0 0x10206000 0 0x1000>; #address-cells = <1>; #size-cells = <1>; + + socinfo_data1: socinfo-data1@40 { + reg = <0x040 0x4>; + }; + + socinfo_data2: socinfo-data2@44 { + reg = <0x044 0x4>; + }; + thermal_calibration: calib@528 { reg = <0x528 0xc>; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 976dc968b3ca..d39c25db042e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -1585,6 +1585,15 @@ reg = <0 0x11f10000 0 0x1000>; #address-cells = <1>; #size-cells = <1>; + + socinfo_data1: socinfo-data1@4c { + reg = <0x04c 0x4>; + }; + + socinfo_data2: socinfo-data2@60 { + reg = <0x060 0x4>; + }; + thermal_calibration: calib@180 { reg = <0x180 0xc>; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi index df0c04f2ba1d..0e2f6fe14081 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -1672,6 +1672,10 @@ reg = <0x59c 0x4>; bits = <0 3>; }; + + socinfo_data1: socinfo-data1@7a0 { + reg = <0x7a0 0x4>; + }; }; mipi_tx0: dsi-phy@11cc0000 { diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 69f4cded5dbb..a329b430429f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -1120,6 +1120,14 @@ #address-cells = <1>; #size-cells = <1>; + socinfo_data1: socinfo-data1@44 { + reg = <0x044 0x4>; + }; + + socinfo_data2: socinfo-data2@50 { + reg = <0x050 0x4>; + }; + lvts_e_data1: data1@1c0 { reg = <0x1c0 0x58>; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index e0ac2e9f5b72..f1926a6afa8f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1686,6 +1686,9 @@ lvts_efuse_data2: lvts2-calib@1d0 { reg = <0x1d0 0x38>; }; + socinfo_data1: socinfo-data1@7a0 { + reg = <0x7a0 0x4>; + }; }; u3phy2: t-phy@11c40000 {