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Fri, 15 Mar 2024 01:35:58 -0700 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 15 Mar 2024 16:34:51 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 15 Mar 2024 16:34:51 +0800 From: To: , , , , CC: , , , , , , , , , , , , , , Subject: [PATCH v2 5/7] ufs: host: mediatek: rename host power control API Date: Fri, 15 Mar 2024 16:34:46 +0800 Message-ID: <20240315083448.7185-6-peter.wang@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240315083448.7185-1-peter.wang@mediatek.com> References: <20240315083448.7185-1-peter.wang@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--8.382800-8.000000 X-TMASE-MatchedRID: Dz2rI8EJB2ASsMJYjeJjbpXi1z8zt1TRVg8Cu6buTGUH8UzOewTxw64T oUk/aSm1G04xakpCTBluGm5dWKYjJW94Ipa1otxoFYJUGv4DL3xo3Yq5PCwLAvNhzIgXtFJV88y Ax0zkDh7IrNi4B9W0wmRsrGzt2UVHWrGyEceiJjOO0rt0LpQGedVeTBbTX7DomyiLZetSf8mfop 0ytGwvXiq2rl3dzGQ1l3+bAt/YFVQrDtKO1nMb87ylVHbseLLr9peJJrwQXnmJjf1mJVm5IF8I4 oUq5Vga X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--8.382800-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: C01B34E67F7175378414B0B793A12B756D2599DB6D4BDD5D41C9AA142BEDD6D22000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240315_013603_630276_43E79BDF X-CRM114-Status: GOOD ( 11.13 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org From: Po-Wen Kao Mediatek host power include two part: 1. ufshci power, which is the main power of ufs host controller. 2. ufshci crypto sram power, which is the power of ufs crypto engine. This host power control is actually control crypto sram power. Rename it for easy maintain. Acked-by: Chun-Hung Wu Reviewed-by: Avri Altman Reviewed-by: Peter Wang Signed-off-by: Peter Wang Signed-off-by: Po-Wen Kao --- drivers/ufs/host/ufs-mediatek-sip.h | 13 +++---------- drivers/ufs/host/ufs-mediatek.c | 4 ++-- 2 files changed, 5 insertions(+), 12 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek-sip.h b/drivers/ufs/host/ufs-mediatek-sip.h index 35d1d5e76a2c..c26513aedee3 100755 --- a/drivers/ufs/host/ufs-mediatek-sip.h +++ b/drivers/ufs/host/ufs-mediatek-sip.h @@ -16,7 +16,7 @@ #define UFS_MTK_SIP_DEVICE_RESET BIT(1) #define UFS_MTK_SIP_CRYPTO_CTRL BIT(2) #define UFS_MTK_SIP_REF_CLK_NOTIFICATION BIT(3) -#define UFS_MTK_SIP_HOST_PWR_CTRL BIT(5) +#define UFS_MTK_SIP_SRAM_PWR_CTRL BIT(5) #define UFS_MTK_SIP_GET_VCC_NUM BIT(6) #define UFS_MTK_SIP_DEVICE_PWR_CTRL BIT(7) @@ -31,13 +31,6 @@ enum ufs_mtk_vcc_num { UFS_VCC_MAX }; -/* - * Host Power Control options - */ -enum { - HOST_PWR_HCI = 0, - HOST_PWR_MPHY -}; /* * SMC call wrapper function @@ -78,8 +71,8 @@ static inline void _ufs_mtk_smc(struct ufs_mtk_smc_arg s) #define ufs_mtk_device_reset_ctrl(high, res) \ ufs_mtk_smc(UFS_MTK_SIP_DEVICE_RESET, &(res), high) -#define ufs_mtk_host_pwr_ctrl(opt, on, res) \ - ufs_mtk_smc(UFS_MTK_SIP_HOST_PWR_CTRL, &(res), opt, on) +#define ufs_mtk_sram_pwr_ctrl(on, res) \ + ufs_mtk_smc(UFS_MTK_SIP_SRAM_PWR_CTRL, &(res), on) #define ufs_mtk_get_vcc_num(res) \ ufs_mtk_smc(UFS_MTK_SIP_GET_VCC_NUM, &(res)) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c index bb5b11185d8a..90523652a6fb 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -1376,7 +1376,7 @@ static int ufs_mtk_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op, if (ufshcd_is_link_off(hba)) ufs_mtk_device_reset_ctrl(0, res); - ufs_mtk_host_pwr_ctrl(HOST_PWR_HCI, false, res); + ufs_mtk_sram_pwr_ctrl(false, res); return 0; fail: @@ -1397,7 +1397,7 @@ static int ufs_mtk_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) ufs_mtk_dev_vreg_set_lpm(hba, false); - ufs_mtk_host_pwr_ctrl(HOST_PWR_HCI, true, res); + ufs_mtk_sram_pwr_ctrl(true, res); err = ufs_mtk_mphy_power_on(hba, true); if (err)