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Thu, 06 Jun 2024 02:26:41 -0700 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Thu, 6 Jun 2024 17:26:38 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Thu, 6 Jun 2024 17:26:38 +0800 From: Shawn Sung To: Chun-Kuang Hu Subject: [PATCH v8 16/16] drm/mediatek: Support CRC in OVL adaptor Date: Thu, 6 Jun 2024 17:26:35 +0800 Message-ID: <20240606092635.27981-17-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240606092635.27981-1-shawn.sung@mediatek.com> References: <20240606092635.27981-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--6.980900-8.000000 X-TMASE-MatchedRID: u2gSivHusvO/gdQC9NfM37dQIb8hCnY+Xru95hSuhjTi7ECA5q90ucCS 2AMm1nQCbjMOm8SwCSYRNd8KRmWUzeVM9fuANPF9A9lly13c/gEraL2mh8ZVKwqiCYa6w8tv7fK xaM2xqkB3h9ijPpALVnm3rlWwtGYxgZi/ORh+nqAMH4SsGvRsA66JG5H2YJq6u6qThyrnanOuvq nb77eCoD2ixCH7D+gZqYdJomSPWScR3RjJbq0tuRIRh9wkXSlFfS0Ip2eEHnz3IzXlXlpamPoLR 4+zsDTtgUicvJ4MChmz0fvt1jaX599wrn/JZI0QeWv5iXuKOgMtI1zDS8Cp0charoVSgHr8 X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--6.980900-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 4D22542C32BF62AA1B2173DFEF22851614B504DCA9A87F67BF480D7AAB4588A02000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240606_022646_949127_7FAD3EA5 X-CRM114-Status: GOOD ( 15.79 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Vetter , Sean Paul , Jason Chen , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, CK Hu , "Nancy . Lin" , linux-mediatek@lists.infradead.org, Bibby Hsieh , Matthias Brugger , Philipp Zabel , Hsiao Chien Sung , David Airlie , linux-arm-kernel@lists.infradead.org, AngeloGioacchino Del Regno Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org From: Hsiao Chien Sung We choose Mixer as CRC generator in OVL adaptor since its frame done event will trigger vblanks, we can know when is safe to retrieve CRC of the frame. In OVL adaptor, there's no image procession after Mixer, unlike the OVL in VDOSYS0, Mixer's CRC will include all the effects that are applied to the frame. Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 5 ++ drivers/gpu/drm/mediatek/mtk_disp_drv.h | 5 ++ .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 35 +++++++++ drivers/gpu/drm/mediatek/mtk_ethdr.c | 72 +++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_ethdr.h | 7 ++ 5 files changed, 124 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c index 07c3b5c5e14e..473460ab3a7a 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c @@ -408,6 +408,11 @@ static const struct mtk_ddp_comp_funcs ddp_ovl_adaptor = { .clk_enable = mtk_ovl_adaptor_clk_enable, .clk_disable = mtk_ovl_adaptor_clk_disable, .config = mtk_ovl_adaptor_config, + .crc_cnt = mtk_ovl_adaptor_crc_cnt, + .crc_entry = mtk_ovl_adaptor_crc_entry, + .crc_read = mtk_ovl_adaptor_crc_read, + .crc_start = mtk_ovl_adaptor_crc_start, + .crc_stop = mtk_ovl_adaptor_crc_stop, .start = mtk_ovl_adaptor_start, .stop = mtk_ovl_adaptor_stop, .layer_nr = mtk_ovl_adaptor_layer_nr, diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h index a03d7a10847a..0ef32bc3b996 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -140,6 +140,11 @@ const u32 *mtk_ovl_adaptor_get_formats(struct device *dev); size_t mtk_ovl_adaptor_get_num_formats(struct device *dev); enum drm_mode_status mtk_ovl_adaptor_mode_valid(struct device *dev, const struct drm_display_mode *mode); +size_t mtk_ovl_adaptor_crc_cnt(struct device *dev); +u32 *mtk_ovl_adaptor_crc_entry(struct device *dev); +void mtk_ovl_adaptor_crc_read(struct device *dev); +void mtk_ovl_adaptor_crc_start(struct device *dev); +void mtk_ovl_adaptor_crc_stop(struct device *dev); void mtk_rdma_bypass_shadow(struct device *dev); int mtk_rdma_clk_enable(struct device *dev); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c index 2b62d6475918..02a617ac8265 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c @@ -207,6 +207,41 @@ void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx, mtk_ethdr_layer_config(ethdr, idx, state, cmdq_pkt); } +size_t mtk_ovl_adaptor_crc_cnt(struct device *dev) +{ + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev); + + return mtk_ethdr_crc_cnt(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]); +} + +u32 *mtk_ovl_adaptor_crc_entry(struct device *dev) +{ + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev); + + return mtk_ethdr_crc_entry(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]); +} + +void mtk_ovl_adaptor_crc_read(struct device *dev) +{ + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev); + + mtk_ethdr_crc_read(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]); +} + +void mtk_ovl_adaptor_crc_start(struct device *dev) +{ + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev); + + mtk_ethdr_crc_start(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]); +} + +void mtk_ovl_adaptor_crc_stop(struct device *dev) +{ + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev); + + mtk_ethdr_crc_stop(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]); +} + void mtk_ovl_adaptor_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediatek/mtk_ethdr.c index d01f65819816..1e6a51979ec6 100644 --- a/drivers/gpu/drm/mediatek/mtk_ethdr.c +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c @@ -25,6 +25,9 @@ #define MIX_FME_CPL_INTEN BIT(1) #define MIX_INTSTA 0x8 #define MIX_EN 0xc +#define MIX_TRIG 0x10 +#define MIX_TRIG_CRC_EN BIT(8) +#define MIX_TRIG_CRC_RST BIT(9) #define MIX_RST 0x14 #define MIX_ROI_SIZE 0x18 #define MIX_DATAPATH_CON 0x1c @@ -40,6 +43,11 @@ #define PREMULTI_SOURCE (3 << 12) #define MIX_L_SRC_SIZE(n) (0x30 + 0x18 * (n)) #define MIX_L_SRC_OFFSET(n) (0x34 + 0x18 * (n)) + +/* CRC register offsets for odd and even lines */ +#define MIX_CRC_ODD 0x110 +#define MIX_CRC_EVEN 0x114 + #define MIX_FUNC_DCM0 0x120 #define MIX_FUNC_DCM1 0x124 #define MIX_FUNC_DCM_ENABLE 0xffffffff @@ -83,6 +91,7 @@ struct mtk_ethdr { void *vblank_cb_data; int irq; struct reset_control *reset_ctl; + struct mtk_crtc_crc crc; }; static const char * const ethdr_clk_str[] = { @@ -101,6 +110,50 @@ static const char * const ethdr_clk_str[] = { "vdo_be_async", }; +static const u32 ethdr_crc_ofs[] = { + MIX_CRC_ODD, + MIX_CRC_EVEN, +}; + +size_t mtk_ethdr_crc_cnt(struct device *dev) +{ + struct mtk_ethdr *priv = dev_get_drvdata(dev); + + return priv->crc.cnt; +} + +u32 *mtk_ethdr_crc_entry(struct device *dev) +{ + struct mtk_ethdr *priv = dev_get_drvdata(dev); + + return priv->crc.va; +} + +void mtk_ethdr_crc_read(struct device *dev) +{ + struct mtk_ethdr *priv = dev_get_drvdata(dev); + + mtk_crtc_read_crc(&priv->crc, priv->ethdr_comp[ETHDR_MIXER].regs); +} + +void mtk_ethdr_crc_start(struct device *dev) +{ + struct mtk_ethdr *priv = dev_get_drvdata(dev); + +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + mtk_crtc_start_crc_cmdq(&priv->crc); +#endif +} + +void mtk_ethdr_crc_stop(struct device *dev) +{ + struct mtk_ethdr *priv = dev_get_drvdata(dev); + +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + mtk_crtc_stop_crc_cmdq(&priv->crc); +#endif +} + void mtk_ethdr_register_vblank_cb(struct device *dev, void (*vblank_cb)(void *), void *vblank_cb_data) @@ -259,6 +312,9 @@ void mtk_ethdr_start(struct device *dev) struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER]; writel(1, mixer->regs + MIX_EN); + + if (priv->crc.cnt) + writel(MIX_TRIG_CRC_EN, mixer->regs + MIX_TRIG); } void mtk_ethdr_stop(struct device *dev) @@ -320,6 +376,9 @@ static int mtk_ethdr_probe(struct platform_device *pdev) if (!priv) return -ENOMEM; + mtk_crtc_init_crc(&priv->crc, ethdr_crc_ofs, ARRAY_SIZE(ethdr_crc_ofs), + MIX_TRIG, MIX_TRIG_CRC_RST); + for (i = 0; i < ETHDR_ID_MAX; i++) { priv->ethdr_comp[i].dev = dev; priv->ethdr_comp[i].regs = of_iomap(dev->of_node, i); @@ -328,6 +387,16 @@ static int mtk_ethdr_probe(struct platform_device *pdev) &priv->ethdr_comp[i].cmdq_base, i); if (ret) dev_dbg(dev, "get mediatek,gce-client-reg fail!\n"); + + if (i == ETHDR_MIXER) { + if (of_property_read_u32_index(dev->of_node, + "mediatek,gce-events", i, + &priv->crc.cmdq_event)) { + dev_warn(dev, "failed to get gce-events for crc\n"); + } + priv->crc.cmdq_reg = &priv->ethdr_comp[i].cmdq_base; + mtk_crtc_create_crc_cmdq(dev, &priv->crc); + } #endif dev_dbg(dev, "[DRM]regs:0x%p, node:%d\n", priv->ethdr_comp[i].regs, i); } @@ -368,6 +437,9 @@ static int mtk_ethdr_probe(struct platform_device *pdev) static void mtk_ethdr_remove(struct platform_device *pdev) { + struct mtk_ethdr *priv = dev_get_drvdata(&pdev->dev); + + mtk_crtc_destroy_crc(&priv->crc); component_del(&pdev->dev, &mtk_ethdr_component_ops); } diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.h b/drivers/gpu/drm/mediatek/mtk_ethdr.h index 81af9edea3f7..6c479c460ac0 100644 --- a/drivers/gpu/drm/mediatek/mtk_ethdr.h +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.h @@ -22,4 +22,11 @@ void mtk_ethdr_register_vblank_cb(struct device *dev, void mtk_ethdr_unregister_vblank_cb(struct device *dev); void mtk_ethdr_enable_vblank(struct device *dev); void mtk_ethdr_disable_vblank(struct device *dev); + +size_t mtk_ethdr_crc_cnt(struct device *dev); +u32 *mtk_ethdr_crc_entry(struct device *dev); +void mtk_ethdr_crc_read(struct device *dev); +void mtk_ethdr_crc_start(struct device *dev); +void mtk_ethdr_crc_stop(struct device *dev); + #endif