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([178.233.24.52]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42286fe7670sm38110205e9.6.2024.06.12.13.12.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Jun 2024 13:12:21 -0700 (PDT) From: Alper Nebi Yasak To: AngeloGioacchino Del Regno , linux-mediatek@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Stephen Boyd , Rob Herring , devicetree@vger.kernel.org, Michael Turquette , =?utf-8?q?Uwe_Kleine-K=C3=B6ni?= =?utf-8?q?g?= , Conor Dooley , linux-arm-kernel@lists.infradead.org, Chen-Yu Tsai , Krzysztof Kozlowski , Matthias Brugger , linux-clk@vger.kernel.org, Alper Nebi Yasak Subject: [PATCH RESEND v2 2/2] arm64: dts: mediatek: mt8173: Fix timer 13 MHz clock description Date: Wed, 12 Jun 2024 23:11:01 +0300 Message-ID: <20240612201211.91683-2-alpernebiyasak@gmail.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240612201211.91683-1-alpernebiyasak@gmail.com> References: <20240612201211.91683-1-alpernebiyasak@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240612_131226_536990_4245967E X-CRM114-Status: GOOD ( 15.47 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org A previous patch fixes an issue with the mt8173-infracfg clock driver when working as a module, but has the side effect of skipping set up of CLK_INFRA_CLK_13M in that case. This clock is used by the timer device. Similar to the MT8183, MT8192, MT8195 and MT8186 cases [1], change the input clock of the timer block a fixed factor divide-by-2 clock that takes the 26 MHz oscillator as its input. Also remove the RTC clock from the timer node while we're here. According to commit 59311b19d7f63 ("clocksource/drivers/timer-mediatek: Add system timer bindings") it is no longer used. [1] https://lore.kernel.org/all/20221201084229.3464449-1-wenst@chromium.org/ Signed-off-by: Alper Nebi Yasak --- Tested on a MT8173 Chromebook. But I'm not sure I understand all of this, so review with a pinch of salt. Changes in v2: - Add this patch arch/arm64/boot/dts/mediatek/mt8173.dtsi | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 3458be7f7f61..809b379b6818 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -244,6 +244,15 @@ psci { cpu_on = <0x84000003>; }; + clk13m: fixed-factor-clock-13m { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clk26m>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "clk13m"; + }; + clk26m: oscillator0 { compatible = "fixed-clock"; #clock-cells = <0>; @@ -530,8 +539,7 @@ timer: timer@10008000 { "mediatek,mt6577-timer"; reg = <0 0x10008000 0 0x1000>; interrupts = ; - clocks = <&infracfg CLK_INFRA_CLK_13M>, - <&topckgen CLK_TOP_RTC_SEL>; + clocks = <&clk13m>; }; pwrap: pwrap@1000d000 {