From patchwork Sun Jun 16 08:29:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hsiao Chien Sung via B4 Relay X-Patchwork-Id: 13699471 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B9FCDC27C6E for ; Sun, 16 Jun 2024 08:30:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Reply-To:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To: References:Message-Id:Content-Transfer-Encoding:Content-Type:MIME-Version: Subject:Date:From:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=Wuio+3ff+GmYR44kEdIDVwte42nZ4JQztIqpSzJxJVg=; b=dIyV7BqgQxMY2a/Uh5lF26Vf5o xY0gW0taClWv+DEEizBxFgv6JYqvVP7l/Od5xLdw28RPExJeZN0JWC5jHSOuEE0BsxFAXz4L2f1k/ 2MmfzIz3UhFhpp18o69pAbjsCjQQdCGu2JN0nLcnVTa1xj7VQsBgmLiNlffaTsUqd3HT4+yMkBsrZ i6Eg4zOAK0nAPq0fFqjcrDN/As1/GFx4j0Kh62TNda6KKoaZ+HYz0BiSa2EvS3Ymk8mUSVh8g3eXv 43iKTa16fSErW9bcOBB1nW+xtRE3nc7JLlwvWG681cYjoyh8g8fgEtnPHoIW2hVBYKbTZ8wmV4lWG BbXGUzGQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sIlHM-000000078Sw-1tpp; Sun, 16 Jun 2024 08:30:24 +0000 Received: from sin.source.kernel.org ([2604:1380:40e1:4800::1]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sIlGJ-000000077jC-2otI; Sun, 16 Jun 2024 08:29:25 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sin.source.kernel.org (Postfix) with ESMTP id CE6C8CE0B53; Sun, 16 Jun 2024 08:29:16 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPS id D83F2C4AF1D; Sun, 16 Jun 2024 08:29:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1718526554; bh=Rxn1gnGGokSSuKzKIeIUyeSaIESIT/g/wWVSlGfjLDk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=oB/nmopMltO0EzxN7IWfWOREtAtuBDPyJoyDW1OHbY3/tPGezT2N39kjs99BtMKkk /OdZsUi0y6XMzHpcBfWQyD/dBKU7IvUUvylmaC8x+SU4N+CjCKiGg+V6RsZZuSClpn kqtVL7ODGCLoeiT7dDSR3+gcaWjc1X4Tm+S9WV+CRRYGaOCNlynOs4nmNYjA9Gr2TC 8SzE34f1NHI68o6/PjwpuQoESbDMXqfmHuMW5qkhLjD7ewFz0QvcLGm0E9sk86NwD/ cl5bd2yYFRogWTWDOHB3GUs2vdpE0IMgSwX1wtiQAPH4/WFEwpEHQi7/OXrMd6p41n 79WBVJOaxXbgQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id C512BC2BA15; Sun, 16 Jun 2024 08:29:14 +0000 (UTC) From: Hsiao Chien Sung via B4 Relay Date: Sun, 16 Jun 2024 16:29:11 +0800 Subject: [PATCH 01/13] soc: mediatek: Disable 9-bit alpha in ETHDR MIME-Version: 1.0 Message-Id: <20240616-mediatek-drm-next-v1-1-7e8f9cf785d8@mediatek.com> References: <20240616-mediatek-drm-next-v1-0-7e8f9cf785d8@mediatek.com> In-Reply-To: <20240616-mediatek-drm-next-v1-0-7e8f9cf785d8@mediatek.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno , CK Hu , Bibby Hsieh , Daniel Kurtz , YT Shen , Mao Huang , "Nancy.Lin" Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Hsiao Chien Sung X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1718526553; l=2103; i=shawn.sung@mediatek.com; s=20240616; h=from:subject:message-id; bh=AhpL6mafGPf92ATlXUF9GJd5xSZP0P96bzGL4snlDgc=; b=wItu85Eor8vZDTd2CEgLbljnmpGnci2Gj9uQnt0nUPAZYN+tofn1d7wu0+uu4ryK64HWsaHAM 7xOuKPpTiFkCxlEy11K8dLZRwBcUGjA6kbqDe+Fh9CG9L6KWA6cHKaw X-Developer-Key: i=shawn.sung@mediatek.com; a=ed25519; pk=lq1w8BuWDINX+4JHjGHhhbAU5ICP+cL9VCj7wn+cEDA= X-Endpoint-Received: by B4 Relay for shawn.sung@mediatek.com/20240616 with auth_id=172 X-Original-From: Hsiao Chien Sung X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240616_012920_212916_373A3DE9 X-CRM114-Status: GOOD ( 11.86 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: shawn.sung@mediatek.com Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org From: Hsiao Chien Sung When 9-bit alpha is enabled, its value will be converted from 0-255 to 0-256 (255 = not defined). This is designed for special HDR related calculation, which should be disabled by default, otherwise, alpha blending will not work correctly. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_ethdr.c | 3 +-- drivers/soc/mediatek/mtk-mmsys.c | 1 + 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediatek/mtk_ethdr.c index 156c6ff547e8..d7d16482c947 100644 --- a/drivers/gpu/drm/mediatek/mtk_ethdr.c +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c @@ -50,7 +50,6 @@ #define MIXER_INX_MODE_BYPASS 0 #define MIXER_INX_MODE_EVEN_EXTEND 1 -#define DEFAULT_9BIT_ALPHA 0x100 #define MIXER_ALPHA_AEN BIT(8) #define MIXER_ALPHA 0xff #define ETHDR_CLK_NUM 13 @@ -169,7 +168,7 @@ void mtk_ethdr_layer_config(struct device *dev, unsigned int idx, alpha_con = MIXER_ALPHA_AEN | MIXER_ALPHA; mtk_mmsys_mixer_in_config(priv->mmsys_dev, idx + 1, alpha_con ? false : true, - DEFAULT_9BIT_ALPHA, + MIXER_ALPHA, pending->x & 1 ? MIXER_INX_MODE_EVEN_EXTEND : MIXER_INX_MODE_BYPASS, align_width / 2 - 1, cmdq_pkt); diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index f370f4ec4b88..938240714e54 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -236,6 +236,7 @@ void mtk_mmsys_mixer_in_config(struct device *dev, int idx, bool alpha_sel, u16 mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_ALPHA + (idx - 1) * 4, ~0, alpha << 16 | alpha, cmdq_pkt); + mtk_mmsys_update_bits(mmsys, MT8195_VDO1_HDR_TOP_CFG, BIT(15 + idx), 0, cmdq_pkt); mtk_mmsys_update_bits(mmsys, MT8195_VDO1_HDR_TOP_CFG, BIT(19 + idx), alpha_sel << (19 + idx), cmdq_pkt); mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_PAD + (idx - 1) * 4,