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a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240627_033242_772251_DEF5BEEC X-CRM114-Status: GOOD ( 10.77 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Document sprd,sc9863a-glbregs compatible already used in DTS and other bindings example. Reviewed-by: Rob Herring (Arm) Reviewed-by: Baolin Wang Signed-off-by: Krzysztof Kozlowski --- .../bindings/soc/sprd/sprd,sc9863a-glbregs.yaml | 55 ++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/sprd/sprd,sc9863a-glbregs.yaml b/Documentation/devicetree/bindings/soc/sprd/sprd,sc9863a-glbregs.yaml new file mode 100644 index 000000000000..49add564e5e1 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/sprd/sprd,sc9863a-glbregs.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/sprd/sprd,sc9863a-glbregs.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SC9863A Syscon + +maintainers: + - Orson Zhai + - Baolin Wang + - Chunyan Zhang + +properties: + compatible: + items: + - const: sprd,sc9863a-glbregs + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + ranges: true + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + +patternProperties: + "@[0-9a-f]+$": + $ref: /schemas/clock/sprd,sc9863a-clk.yaml + description: Clock controllers + +additionalProperties: false + +examples: + - | + syscon@20e00000 { + compatible = "sprd,sc9863a-glbregs", "syscon", "simple-mfd"; + reg = <0x20e00000 0x4000>; + ranges = <0 0x20e00000 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + apahb_gate: apahb-gate@0 { + compatible = "sprd,sc9863a-apahb-gate"; + reg = <0x0 0x1020>; + #clock-cells = <1>; + }; + }; + +...