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AJvYcCVq738WPRSA3ESilIKz5Quh/6+mLgvGGf5VGfIlOAjVHHRMYhEQLPEczqQ68Eam+FriavCD+x7xLMilWE9ayFpgiMlBBYkSjrch/Dm5lmIrBgSE X-Gm-Message-State: AOJu0YzrJsWZvf71iCxA9sVa+X2XDKAAtopEhcrGf4y1uGWoMoMBuyzk CRHlpJnP5FWQXefaMQ6mxGxo3cJA8OdGH8UyDBeFTvMRMdVVHTTFYi0WiN03Qw== X-Google-Smtp-Source: AGHT+IEXToHGxpVGoEz8ifOQW7GTguBEcp/knYddtQGBeIRtKWqgX5quU9fqgATZlNifTQih+UOzCA== X-Received: by 2002:a05:6a20:b2a9:b0:1be:c2af:5626 with SMTP id adf61e73a8af0-1bec2af566dmr2984750637.4.1719475179932; Thu, 27 Jun 2024 00:59:39 -0700 (PDT) Received: from localhost.localdomain ([2403:5816:cd6c:0:6d45:ae2f:1ead:bd58]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1faac9c4cf4sm7181895ad.290.2024.06.27.00.59.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jun 2024 00:59:39 -0700 (PDT) From: Leith Bade To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, frank-w@public-files.de Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, didi.debian@cknow.org, Leith Bade Subject: [PATCH 1/4] arm64: dts: mediatek: mt7986: fix the switch reset line on BPI-R3 Date: Thu, 27 Jun 2024 17:58:53 +1000 Message-Id: <20240627075856.2314804-2-leith@bade.nz> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240627075856.2314804-1-leith@bade.nz> References: <20240627075856.2314804-1-leith@bade.nz> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240627_005945_896811_B6AE2EB3 X-CRM114-Status: GOOD ( 11.59 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org The current GPIO definition for the MT7531 switch reset line incorrectly specifies a pin GPIO_0 (GPIO5) that is connected to the boot mode selection DIP switch (SW1). In the public schematic for the BPI-R3 (titled "BPI-R3-MT7986A", revision "V1.1", sheet 4), the SPI1_CS (GPIO32) pin of the MT7986 (U1E) is connected to the GbE_RESET net. Frank Wunderlich has told me, via the Banana Pi forum, that this GbE_RESET net connects to the MT7531 reset line in the private part of the shematic he has a copy of. Signed-off-by: Leith Bade Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts index ed79ad1ae871..951612ea1e66 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts @@ -206,7 +206,7 @@ switch: switch@31 { interrupt-controller; #interrupt-cells = <1>; interrupts-extended = <&pio 66 IRQ_TYPE_LEVEL_HIGH>; - reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pio 32 GPIO_ACTIVE_HIGH>; }; };