From patchwork Tue Jul 30 08:24:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liju-clr Chen X-Patchwork-Id: 13747012 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2996EC3DA61 for ; Tue, 30 Jul 2024 08:28:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type:MIME-Version: References:In-Reply-To:Message-ID:Date:Subject:CC:To:From:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=raoc6D10ZA9gdrP1WQWEpkGLNRNOcd69vFk4zCxJ5PA=; b=oFlCU4F94a/UWeVBLF7f1K4Zgb oZVkzfBPvpVCyuL9Aj1vH0LcwcgkkNDQn0hpoBYZzM5J8x6DrN56q+vpYCs8XUlb/18T85ZZMRgKW btpq4va5d8VvX8icxnXgLC6w/Zpod+3Zo1kLJP5eVzoOVORCgkVa0/Nvd00lwMIBkCIBJrlqWjIt3 Z41t8mWwSvozAQJIR1VH40nNzgT7cOhAY6b6jY9FNhhGEjhIHfRYMHfuGzaJihb7CnQSLD9B0dWVN 99PUc7Gc94cTUhvvzI3BI99EJvMpI0e+oe2+r2E/59+0Qqlu6v5nVTIpAdd8PFrFap2E8iOE7XX7M FgNzYROQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sYiE6-0000000EG75-3UNR; Tue, 30 Jul 2024 08:28:58 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sYiA3-0000000EE5u-3wAp; Tue, 30 Jul 2024 08:24:51 +0000 X-UUID: 2b44e4ba4e4d11ef955bff358274dad2-20240730 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=raoc6D10ZA9gdrP1WQWEpkGLNRNOcd69vFk4zCxJ5PA=; b=AAMa5CZarYO0sKuaabJ5YNLW72Vr/wMdjl6p+z1MgreDJSTM7zij8PG1i1u8sagZtITGh/h7hU4pN388dEMa/OyaagXTT8XnjOVo1pw1GPrSFBeHoX1bVSqPg80PuEJq5t0pHQoOc/YDirL3DZd2LF1AQtK9Xkp9u3yiBk7/dZ8=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.41,REQID:1b4a26af-5a0b-4820-95f9-f32ee0b6ed21,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:6dc6a47,CLOUDID:57970a0e-46b0-425a-97d3-4623fe284021,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES :1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: 2b44e4ba4e4d11ef955bff358274dad2-20240730 Received: from mtkmbs09n2.mediatek.inc [(172.21.101.94)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1825639968; Tue, 30 Jul 2024 01:24:41 -0700 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by MTKMBS09N2.mediatek.inc (172.21.101.94) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Tue, 30 Jul 2024 01:24:38 -0700 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Tue, 30 Jul 2024 16:24:38 +0800 From: Liju-clr Chen To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet , Catalin Marinas , Will Deacon , Steven Rostedt , Masami Hiramatsu , Mathieu Desnoyers , Richard Cochran , Matthias Brugger , AngeloGioacchino Del Regno , Liju-clr Chen , Yingshiuan Pan , Ze-yu Wang CC: , , , , , , , Shawn Hsiao , PeiLun Suei , Chi-shen Yeh , Kevenny Hsieh Subject: [PATCH v12 13/24] virt: geniezone: Add dtb config support Date: Tue, 30 Jul 2024 16:24:25 +0800 Message-ID: <20240730082436.9151-14-liju-clr.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240730082436.9151-1-liju-clr.chen@mediatek.com> References: <20240730082436.9151-1-liju-clr.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240730_012448_325647_4C44235E X-CRM114-Status: GOOD ( 16.37 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org From: Jerry Wang Hypervisor might need to know the accurate address and size of dtb passed from userspace. And then hypervisor would parse the dtb and get vm information. Signed-off-by: Jerry Wang Signed-off-by: Yi-De Wu Signed-off-by: Liju Chen --- arch/arm64/geniezone/gzvm_arch_common.h | 2 ++ arch/arm64/geniezone/vm.c | 9 +++++++++ drivers/virt/geniezone/gzvm_vm.c | 10 ++++++++++ include/linux/soc/mediatek/gzvm_drv.h | 1 + include/uapi/linux/gzvm.h | 14 ++++++++++++++ 5 files changed, 36 insertions(+) diff --git a/arch/arm64/geniezone/gzvm_arch_common.h b/arch/arm64/geniezone/gzvm_arch_common.h index dabd11438e94..4366618cdc0a 100644 --- a/arch/arm64/geniezone/gzvm_arch_common.h +++ b/arch/arm64/geniezone/gzvm_arch_common.h @@ -23,6 +23,7 @@ enum { GZVM_FUNC_ENABLE_CAP = 13, GZVM_FUNC_INFORM_EXIT = 14, GZVM_FUNC_MEMREGION_PURPOSE = 15, + GZVM_FUNC_SET_DTB_CONFIG = 16, NR_GZVM_FUNC, }; @@ -46,6 +47,7 @@ enum { #define MT_HVC_GZVM_ENABLE_CAP GZVM_HCALL_ID(GZVM_FUNC_ENABLE_CAP) #define MT_HVC_GZVM_INFORM_EXIT GZVM_HCALL_ID(GZVM_FUNC_INFORM_EXIT) #define MT_HVC_GZVM_MEMREGION_PURPOSE GZVM_HCALL_ID(GZVM_FUNC_MEMREGION_PURPOSE) +#define MT_HVC_GZVM_SET_DTB_CONFIG GZVM_HCALL_ID(GZVM_FUNC_SET_DTB_CONFIG) #define GIC_V3_NR_LRS 16 diff --git a/arch/arm64/geniezone/vm.c b/arch/arm64/geniezone/vm.c index c20a2ded2a4f..00c74a4bcfd7 100644 --- a/arch/arm64/geniezone/vm.c +++ b/arch/arm64/geniezone/vm.c @@ -154,6 +154,15 @@ int gzvm_arch_memregion_purpose(struct gzvm *gzvm, mem->flags, 0, 0, 0, &res); } +int gzvm_arch_set_dtb_config(struct gzvm *gzvm, struct gzvm_dtb_config *cfg) +{ + struct arm_smccc_res res; + + return gzvm_hypcall_wrapper(MT_HVC_GZVM_SET_DTB_CONFIG, gzvm->vm_id, + cfg->dtb_addr, cfg->dtb_size, 0, 0, 0, 0, + &res); +} + static int gzvm_vm_arch_enable_cap(struct gzvm *gzvm, struct gzvm_enable_cap *cap, struct arm_smccc_res *res) diff --git a/drivers/virt/geniezone/gzvm_vm.c b/drivers/virt/geniezone/gzvm_vm.c index dd2de6e3bcde..5ae5abff2955 100644 --- a/drivers/virt/geniezone/gzvm_vm.c +++ b/drivers/virt/geniezone/gzvm_vm.c @@ -281,6 +281,16 @@ static long gzvm_vm_ioctl(struct file *filp, unsigned int ioctl, ret = gzvm_vm_ioctl_enable_cap(gzvm, &cap, argp); break; } + case GZVM_SET_DTB_CONFIG: { + struct gzvm_dtb_config cfg; + + if (copy_from_user(&cfg, argp, sizeof(cfg))) { + ret = -EFAULT; + goto out; + } + ret = gzvm_arch_set_dtb_config(gzvm, &cfg); + break; + } default: ret = -ENOTTY; } diff --git a/include/linux/soc/mediatek/gzvm_drv.h b/include/linux/soc/mediatek/gzvm_drv.h index 3c2b5d9071c6..982463eea4f6 100644 --- a/include/linux/soc/mediatek/gzvm_drv.h +++ b/include/linux/soc/mediatek/gzvm_drv.h @@ -181,6 +181,7 @@ void gzvm_vm_irqfd_release(struct gzvm *gzvm); int gzvm_arch_memregion_purpose(struct gzvm *gzvm, struct gzvm_userspace_memory_region *mem); +int gzvm_arch_set_dtb_config(struct gzvm *gzvm, struct gzvm_dtb_config *args); int gzvm_init_ioeventfd(struct gzvm *gzvm); int gzvm_ioeventfd(struct gzvm *gzvm, struct gzvm_ioeventfd *args); diff --git a/include/uapi/linux/gzvm.h b/include/uapi/linux/gzvm.h index 6e102cbfec98..7aec4adf2206 100644 --- a/include/uapi/linux/gzvm.h +++ b/include/uapi/linux/gzvm.h @@ -364,4 +364,18 @@ struct gzvm_ioeventfd { #define GZVM_IOEVENTFD _IOW(GZVM_IOC_MAGIC, 0x79, struct gzvm_ioeventfd) +/** + * struct gzvm_dtb_config: store address and size of dtb passed from userspace + * + * @dtb_addr: dtb address set by VMM (guset memory) + * @dtb_size: dtb size + */ +struct gzvm_dtb_config { + __u64 dtb_addr; + __u64 dtb_size; +}; + +#define GZVM_SET_DTB_CONFIG _IOW(GZVM_IOC_MAGIC, 0xff, \ + struct gzvm_dtb_config) + #endif /* __GZVM_H__ */