Message ID | 20240821092659.1226250-3-rohiagar@chromium.org (mailing list archive) |
---|---|
State | New |
Headers | show
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[34.143.174.185]) by smtp.gmail.com with UTF8SMTPSA id d9443c01a7336-201f038e33asm89674035ad.219.2024.08.21.02.27.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 21 Aug 2024 02:27:22 -0700 (PDT) From: Rohit Agarwal <rohiagar@chromium.org> To: chunkuang.hu@kernel.org, p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, ck.hu@mediatek.com, jitao.shi@mediatek.com Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Rohit Agarwal <rohiagar@chromium.org> Subject: [PATCH v2 2/3] arm64: dts: mediatek: mt8186: Add power domain for DPI Date: Wed, 21 Aug 2024 09:26:58 +0000 Message-ID: <20240821092659.1226250-3-rohiagar@chromium.org> X-Mailer: git-send-email 2.46.0.295.g3b9ea8a38a-goog In-Reply-To: <20240821092659.1226250-1-rohiagar@chromium.org> References: <20240821092659.1226250-1-rohiagar@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240821_022724_273915_15408213 X-CRM114-Status: UNSURE ( 8.75 ) X-CRM114-Notice: Please train this message. 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Devicetree updates for MT8186
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expand
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diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi index 4763ed5dc86c..e27c69ec8bdd 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -1824,6 +1824,7 @@ dpi: dpi@1400a000 { assigned-clocks = <&topckgen CLK_TOP_DPI>; assigned-clock-parents = <&topckgen CLK_TOP_TVDPLL_D2>; interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_LOW 0>; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; status = "disabled"; port {
Add power domain phandle to the DPI controller in mediatek mt8186 SoC. Signed-off-by: Rohit Agarwal <rohiagar@chromium.org> --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 1 + 1 file changed, 1 insertion(+)