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X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Herring , Conor Dooley , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Add the vdosys0 display nodes to support the internal display pipeline. Signed-off-by: Fei Shao --- (no changes since v1) arch/arm64/boot/dts/mediatek/mt8188.dtsi | 86 ++++++++++++++++++++++++ 1 file changed, 86 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi index 79bb80f4b7e5..09556225751e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -26,6 +26,7 @@ / { aliases { gce0 = &gce0; gce1 = &gce1; + mutex0 = &mutex0; }; cpus { @@ -2356,6 +2357,71 @@ jpeg_decoder: jpeg-decoder@1a040000 { power-domains = <&spm MT8188_POWER_DOMAIN_VDEC0>; }; + ovl0: ovl@1c000000 { + compatible = "mediatek,mt8188-disp-ovl", "mediatek,mt8183-disp-ovl"; + reg = <0 0x1c000000 0 0x1000>; + clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>; + interrupts = ; + iommus = <&vdo_iommu M4U_PORT_L0_DISP_OVL0_RDMA0>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>; + }; + + rdma0: rdma@1c002000 { + compatible = "mediatek,mt8188-disp-rdma", "mediatek,mt8195-disp-rdma"; + reg = <0 0x1c002000 0 0x1000>; + clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>; + interrupts = ; + iommus = <&vdo_iommu M4U_PORT_L1_DISP_RDMA0>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>; + }; + + color0: color@1c003000 { + compatible = "mediatek,mt8188-disp-color", "mediatek,mt8173-disp-color"; + reg = <0 0x1c003000 0 0x1000>; + clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>; + interrupts = ; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>; + }; + + ccorr0: ccorr@1c004000 { + compatible = "mediatek,mt8188-disp-ccorr", "mediatek,mt8192-disp-ccorr"; + reg = <0 0x1c004000 0 0x1000>; + clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>; + interrupts = ; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>; + }; + + aal0: aal@1c005000 { + compatible = "mediatek,mt8188-disp-aal", "mediatek,mt8183-disp-aal"; + reg = <0 0x1c005000 0 0x1000>; + clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>; + interrupts = ; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>; + }; + + gamma0: gamma@1c006000 { + compatible = "mediatek,mt8188-disp-gamma", "mediatek,mt8195-disp-gamma"; + reg = <0 0x1c006000 0 0x1000>; + clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>; + interrupts = ; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>; + }; + + dither0: dither@1c007000 { + compatible = "mediatek,mt8188-disp-dither", "mediatek,mt8183-disp-dither"; + reg = <0 0x1c007000 0 0x1000>; + clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>; + interrupts = ; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>; + }; + disp_dsi0: dsi@1c008000 { compatible = "mediatek,mt8188-dsi"; reg = <0 0x1c008000 0 0x1000>; @@ -2386,6 +2452,26 @@ disp_dsi1: dsi@1c012000 { status = "disabled"; }; + mutex0: mutex@1c016000 { + compatible = "mediatek,mt8188-disp-mutex"; + reg = <0 0x1c016000 0 0x1000>; + clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>; + interrupts = ; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x6000 0x1000>; + mediatek,gce-events = ; + }; + + postmask0: postmask@1c01a000 { + compatible = "mediatek,mt8188-disp-postmask", + "mediatek,mt8192-disp-postmask"; + reg = <0 0x1c01a000 0 0x1000>; + clocks = <&vdosys0 CLK_VDO0_DISP_POSTMASK0>; + interrupts = ; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xa000 0x1000>; + }; + vdosys0: syscon@1c01d000 { compatible = "mediatek,mt8188-vdosys0", "syscon"; reg = <0 0x1c01d000 0 0x1000>;