| Message ID | 20241203-mt8188-afe-fix-hang-disabled-apll1-clk-v1-1-07cdd7760834@collabora.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | ASoC: mediatek: mt8188: Enable apll1 clock during reg rw to prevent hang | expand |
On Tue, 2024-12-03 at 17:07 -0300, Nícolas F. R. A. Prado wrote: > > Currently, booting the Genio 700 EVK board with the MT8188 sound > platform driver configured as a module (CONFIG_SND_SOC_MT8188=m) > results > in a system hang right when the HW registers for the audio controller > are read: > > mt8188-audio 10b10000.audio-controller: No cache defaults, reading > back from HW > > The hang doesn't occur with the driver configured as builtin as then > the > unused clocks are still enabled. > > Enable the apll1 clock during register read/write to prevent the > hang. > > Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> > --- > sound/soc/mediatek/mt8188/mt8188-afe-clk.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/sound/soc/mediatek/mt8188/mt8188-afe-clk.c > b/sound/soc/mediatek/mt8188/mt8188-afe-clk.c > index > e69c1bb2cb239596dee50b166c20192d5408be10..fb8cf286df3f02ac076528b898f > d0d7a708ec1ea 100644 > --- a/sound/soc/mediatek/mt8188/mt8188-afe-clk.c > +++ b/sound/soc/mediatek/mt8188/mt8188-afe-clk.c > @@ -587,6 +587,8 @@ int mt8188_afe_enable_reg_rw_clk(struct > mtk_base_afe *afe) > mt8188_afe_enable_clk(afe, afe_priv- > >clk[MT8188_CLK_AUD_A1SYS_HP]); > mt8188_afe_enable_clk(afe, afe_priv- > >clk[MT8188_CLK_AUD_A1SYS]); > > + mt8188_afe_enable_clk(afe, afe_priv- > >clk[MT8188_CLK_APMIXED_APLL1]); > + > return 0; > } Hi Nicolas, If I understand correctly, APLL1 should be the parent clock of AUD_A1SYS_HP and AUD_A1SYS, so it should be enabled automatically by CCF. I'm not sure why you resolved the hang issue after enabling APLL1. Could you share more details about the solution? Thanks, Trevor > > @@ -594,6 +596,8 @@ int mt8188_afe_disable_reg_rw_clk(struct > mtk_base_afe *afe) > { > struct mt8188_afe_private *afe_priv = afe->platform_priv; > > + mt8188_afe_disable_clk(afe, afe_priv- > >clk[MT8188_CLK_APMIXED_APLL1]); > + > mt8188_afe_disable_clk(afe, afe_priv- > >clk[MT8188_CLK_AUD_A1SYS]); > mt8188_afe_disable_clk(afe, afe_priv- > >clk[MT8188_CLK_AUD_A1SYS_HP]); > mt8188_afe_disable_clk(afe, afe_priv- > >clk[MT8188_CLK_AUD_AFE]); > > --- > base-commit: b852e1e7a0389ed6168ef1d38eb0bad71a6b11e8 > change-id: 20241203-mt8188-afe-fix-hang-disabled-apll1-clk- > b3c11782cbaf > > Best regards, > -- > Nícolas F. R. A. Prado <nfraprado@collabora.com> > >
diff --git a/sound/soc/mediatek/mt8188/mt8188-afe-clk.c b/sound/soc/mediatek/mt8188/mt8188-afe-clk.c index e69c1bb2cb239596dee50b166c20192d5408be10..fb8cf286df3f02ac076528b898fd0d7a708ec1ea 100644 --- a/sound/soc/mediatek/mt8188/mt8188-afe-clk.c +++ b/sound/soc/mediatek/mt8188/mt8188-afe-clk.c @@ -587,6 +587,8 @@ int mt8188_afe_enable_reg_rw_clk(struct mtk_base_afe *afe) mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS_HP]); mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS]); + mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_APMIXED_APLL1]); + return 0; } @@ -594,6 +596,8 @@ int mt8188_afe_disable_reg_rw_clk(struct mtk_base_afe *afe) { struct mt8188_afe_private *afe_priv = afe->platform_priv; + mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_APMIXED_APLL1]); + mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS]); mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS_HP]); mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_AFE]);
Currently, booting the Genio 700 EVK board with the MT8188 sound platform driver configured as a module (CONFIG_SND_SOC_MT8188=m) results in a system hang right when the HW registers for the audio controller are read: mt8188-audio 10b10000.audio-controller: No cache defaults, reading back from HW The hang doesn't occur with the driver configured as builtin as then the unused clocks are still enabled. Enable the apll1 clock during register read/write to prevent the hang. Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> --- sound/soc/mediatek/mt8188/mt8188-afe-clk.c | 4 ++++ 1 file changed, 4 insertions(+) --- base-commit: b852e1e7a0389ed6168ef1d38eb0bad71a6b11e8 change-id: 20241203-mt8188-afe-fix-hang-disabled-apll1-clk-b3c11782cbaf Best regards,