| Message ID | 20250115-en7581-pcie-pbus-csr-v1-1-40d8fcb9360f@kernel.org (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | PCI: mediatek-gen3: Set PBUS_CSR regs for Airoha EN7581 SoC. | expand |
On Wed, Jan 15, 2025 at 06:32:30PM +0100, Lorenzo Bianconi wrote: > This patch adds the pbus-csr document bindings for EN7581 SoC. Please do not use "This commit/patch/change", but imperative mood. See longer explanation here: https://elixir.bootlin.com/linux/v5.17.1/source/Documentation/process/submitting-patches.rst#L95 > The airoha pbus-csr block provides a configuration interface for the > PBUS controller used to detect if a given address is on PCIE0, PCIE1 or > PCIE2. > > Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> > --- > .../bindings/arm/airoha,en7581-pbus-csr.yaml | 41 ++++++++++++++++++++++ > 1 file changed, 41 insertions(+) > > diff --git a/Documentation/devicetree/bindings/arm/airoha,en7581-pbus-csr.yaml b/Documentation/devicetree/bindings/arm/airoha,en7581-pbus-csr.yaml > new file mode 100644 > index 0000000000000000000000000000000000000000..80b237e195cd3607645efe3fda1eb6152134481c > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/airoha,en7581-pbus-csr.yaml > @@ -0,0 +1,41 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/arm/airoha,en7581-pbus-csr.yaml# arm is only top level bindings and ARM stuff. This is soc. > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Airoha Pbus CSR Controller for EN7581 SoC > + > +maintainers: > + - Lorenzo Bianconi <lorenzo@kernel.org> > + > +description: > + The airoha pbus-csr block provides a configuration interface for the PBUS > + controller used to detect if a given address is on PCIE0, PCIE1 or PCIE2. > + > +properties: > + compatible: > + items: > + - enum: > + - airoha,en7581-pbus-csr Does not fit standard syscon bindings? Best regards, Krzysztof
> On Wed, Jan 15, 2025 at 06:32:30PM +0100, Lorenzo Bianconi wrote: > > This patch adds the pbus-csr document bindings for EN7581 SoC. > > Please do not use "This commit/patch/change", but imperative mood. See > longer explanation here: > https://elixir.bootlin.com/linux/v5.17.1/source/Documentation/process/submitting-patches.rst#L95 ack, I will fix it in v2 > > > The airoha pbus-csr block provides a configuration interface for the > > PBUS controller used to detect if a given address is on PCIE0, PCIE1 or > > PCIE2. > > > > Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> > > --- > > .../bindings/arm/airoha,en7581-pbus-csr.yaml | 41 ++++++++++++++++++++++ > > 1 file changed, 41 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/arm/airoha,en7581-pbus-csr.yaml b/Documentation/devicetree/bindings/arm/airoha,en7581-pbus-csr.yaml > > new file mode 100644 > > index 0000000000000000000000000000000000000000..80b237e195cd3607645efe3fda1eb6152134481c > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/arm/airoha,en7581-pbus-csr.yaml > > @@ -0,0 +1,41 @@ > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/arm/airoha,en7581-pbus-csr.yaml# > > arm is only top level bindings and ARM stuff. This is soc. in this case we should create an airoha folder in 'Documentation/devicetree/bindings/soc', correct? > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Airoha Pbus CSR Controller for EN7581 SoC > > + > > +maintainers: > > + - Lorenzo Bianconi <lorenzo@kernel.org> > > + > > +description: > > + The airoha pbus-csr block provides a configuration interface for the PBUS > > + controller used to detect if a given address is on PCIE0, PCIE1 or PCIE2. > > + > > +properties: > > + compatible: > > + items: > > + - enum: > > + - airoha,en7581-pbus-csr > > Does not fit standard syscon bindings? I think standard syscon is fine. In this case we could drop this patch. Agree? Regards, Lorenzo > > Best regards, > Krzysztof >
On 01/02/2025 13:16, Lorenzo Bianconi wrote: >>> +maintainers: >>> + - Lorenzo Bianconi <lorenzo@kernel.org> >>> + >>> +description: >>> + The airoha pbus-csr block provides a configuration interface for the PBUS >>> + controller used to detect if a given address is on PCIE0, PCIE1 or PCIE2. >>> + >>> +properties: >>> + compatible: >>> + items: >>> + - enum: >>> + - airoha,en7581-pbus-csr >> >> Does not fit standard syscon bindings? > > I think standard syscon is fine. In this case we could drop this patch. Agree? Yes. Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/arm/airoha,en7581-pbus-csr.yaml b/Documentation/devicetree/bindings/arm/airoha,en7581-pbus-csr.yaml new file mode 100644 index 0000000000000000000000000000000000000000..80b237e195cd3607645efe3fda1eb6152134481c --- /dev/null +++ b/Documentation/devicetree/bindings/arm/airoha,en7581-pbus-csr.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/airoha,en7581-pbus-csr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha Pbus CSR Controller for EN7581 SoC + +maintainers: + - Lorenzo Bianconi <lorenzo@kernel.org> + +description: + The airoha pbus-csr block provides a configuration interface for the PBUS + controller used to detect if a given address is on PCIE0, PCIE1 or PCIE2. + +properties: + compatible: + items: + - enum: + - airoha,en7581-pbus-csr + - const: syscon + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + syscon@1fbe3400 { + compatible = "airoha,en7581-pbus-csr", "syscon"; + reg = <0x0 0x1fbe3400 0x0 0xff>; + }; + };
This patch adds the pbus-csr document bindings for EN7581 SoC. The airoha pbus-csr block provides a configuration interface for the PBUS controller used to detect if a given address is on PCIE0, PCIE1 or PCIE2. Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> --- .../bindings/arm/airoha,en7581-pbus-csr.yaml | 41 ++++++++++++++++++++++ 1 file changed, 41 insertions(+)