| Message ID | 20250211113409.1517534-11-angelogioacchino.delregno@collabora.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Add support for MT8195/88 DPI, HDMIv2 and DDCv2 | expand |
On Tue, 2025-02-11 at 12:33 +0100, AngeloGioacchino Del Regno wrote: > External email : Please do not click links or open attachments until you have verified the sender or the content. > > > Add support for the DPI block found in the MT8195 and MT8188 SoCs. > Inside of the SoC, this block is directly connected to the HDMI IP. > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > --- > drivers/gpu/drm/mediatek/mtk_dpi.c | 24 ++++++++++++++++++++++++ > drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 6 ++++++ > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 ++ > 3 files changed, 32 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c > index 67504eb874d2..e4b52ffc4414 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dpi.c > +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c > @@ -1049,6 +1049,8 @@ static const struct mtk_dpi_factor dpi_factor_mt8195_dp_intf[] = { > { 70000 - 1, 4 }, { 200000 - 1, 2 }, { U32_MAX, 1 } > }; > > +static const struct mtk_dpi_factor dpi_factor_mt8195_dpi = { U32_MAX, 1 }; > + > static const struct mtk_dpi_conf mt8173_conf = { > .dpi_factor = dpi_factor_mt8173, > .num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8173), > @@ -1141,6 +1143,27 @@ static const struct mtk_dpi_conf mt8192_conf = { > .csc_enable_bit = CSC_ENABLE, > }; > > +static const struct mtk_dpi_conf mt8195_conf = { > + .dpi_factor = &dpi_factor_mt8195_dpi, mt8195 dpi would not use dpi_factor, so let it be NULL and drop dpi_factor_mt8195_dpi. After this, Reviewed-by: CK Hu <ck.hu@mediatek.com> > + .num_dpi_factor = 1, > + .max_clock_khz = 594000, > + .output_fmts = mt8183_output_fmts, > + .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts), > + .pixels_per_iter = 1, > + .is_ck_de_pol = true, > + .swap_input_support = true, > + .support_direct_pin = true, > + .dimension_mask = HPW_MASK, > + .hvsize_mask = HSIZE_MASK, > + .channel_swap_shift = CH_SWAP, > + .yuv422_en_bit = YUV422_EN, > + .csc_enable_bit = CSC_ENABLE, > + .input_2p_en_bit = DPI_INPUT_2P_EN, > + .clocked_by_hdmi = true, > + .input_2pixel = true, > + .output_1pixel = true, > +}; > + > static const struct mtk_dpi_conf mt8195_dpintf_conf = { > .dpi_factor = dpi_factor_mt8195_dp_intf, > .num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8195_dp_intf), > @@ -1245,6 +1268,7 @@ static const struct of_device_id mtk_dpi_of_ids[] = { > { .compatible = "mediatek,mt8188-dp-intf", .data = &mt8195_dpintf_conf }, > { .compatible = "mediatek,mt8192-dpi", .data = &mt8192_conf }, > { .compatible = "mediatek,mt8195-dp-intf", .data = &mt8195_dpintf_conf }, > + { .compatible = "mediatek,mt8195-dpi", .data = &mt8195_conf }, > { /* sentinel */ }, > }; > MODULE_DEVICE_TABLE(of, mtk_dpi_of_ids); > diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h > index a0b1d18bbbf7..3c24d9e9f241 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h > +++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h > @@ -40,6 +40,12 @@ > #define FAKE_DE_LEVEN BIT(21) > #define FAKE_DE_RODD BIT(22) > #define FAKE_DE_REVEN BIT(23) > + > +/* DPI_CON: DPI instances */ > +#define DPI_OUTPUT_1T1P_EN BIT(24) > +#define DPI_INPUT_2P_EN BIT(25) > + > +/* DPI_CON: DPINTF instances */ > #define DPINTF_YUV422_EN BIT(24) > #define DPINTF_CSC_ENABLE BIT(26) > #define DPINTF_INPUT_2P_EN BIT(29) > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > index f22ad2882697..772c3d0f5d14 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > @@ -810,6 +810,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { > .data = (void *)MTK_DPI }, > { .compatible = "mediatek,mt8195-dp-intf", > .data = (void *)MTK_DP_INTF }, > + { .compatible = "mediatek,mt8195-dpi", > + .data = (void *)MTK_DPI }, > { .compatible = "mediatek,mt2701-dsi", > .data = (void *)MTK_DSI }, > { .compatible = "mediatek,mt8173-dsi", > -- > 2.48.1 >
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 67504eb874d2..e4b52ffc4414 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -1049,6 +1049,8 @@ static const struct mtk_dpi_factor dpi_factor_mt8195_dp_intf[] = { { 70000 - 1, 4 }, { 200000 - 1, 2 }, { U32_MAX, 1 } }; +static const struct mtk_dpi_factor dpi_factor_mt8195_dpi = { U32_MAX, 1 }; + static const struct mtk_dpi_conf mt8173_conf = { .dpi_factor = dpi_factor_mt8173, .num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8173), @@ -1141,6 +1143,27 @@ static const struct mtk_dpi_conf mt8192_conf = { .csc_enable_bit = CSC_ENABLE, }; +static const struct mtk_dpi_conf mt8195_conf = { + .dpi_factor = &dpi_factor_mt8195_dpi, + .num_dpi_factor = 1, + .max_clock_khz = 594000, + .output_fmts = mt8183_output_fmts, + .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts), + .pixels_per_iter = 1, + .is_ck_de_pol = true, + .swap_input_support = true, + .support_direct_pin = true, + .dimension_mask = HPW_MASK, + .hvsize_mask = HSIZE_MASK, + .channel_swap_shift = CH_SWAP, + .yuv422_en_bit = YUV422_EN, + .csc_enable_bit = CSC_ENABLE, + .input_2p_en_bit = DPI_INPUT_2P_EN, + .clocked_by_hdmi = true, + .input_2pixel = true, + .output_1pixel = true, +}; + static const struct mtk_dpi_conf mt8195_dpintf_conf = { .dpi_factor = dpi_factor_mt8195_dp_intf, .num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8195_dp_intf), @@ -1245,6 +1268,7 @@ static const struct of_device_id mtk_dpi_of_ids[] = { { .compatible = "mediatek,mt8188-dp-intf", .data = &mt8195_dpintf_conf }, { .compatible = "mediatek,mt8192-dpi", .data = &mt8192_conf }, { .compatible = "mediatek,mt8195-dp-intf", .data = &mt8195_dpintf_conf }, + { .compatible = "mediatek,mt8195-dpi", .data = &mt8195_conf }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, mtk_dpi_of_ids); diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h index a0b1d18bbbf7..3c24d9e9f241 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h +++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h @@ -40,6 +40,12 @@ #define FAKE_DE_LEVEN BIT(21) #define FAKE_DE_RODD BIT(22) #define FAKE_DE_REVEN BIT(23) + +/* DPI_CON: DPI instances */ +#define DPI_OUTPUT_1T1P_EN BIT(24) +#define DPI_INPUT_2P_EN BIT(25) + +/* DPI_CON: DPINTF instances */ #define DPINTF_YUV422_EN BIT(24) #define DPINTF_CSC_ENABLE BIT(26) #define DPINTF_INPUT_2P_EN BIT(29) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index f22ad2882697..772c3d0f5d14 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -810,6 +810,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { .data = (void *)MTK_DPI }, { .compatible = "mediatek,mt8195-dp-intf", .data = (void *)MTK_DP_INTF }, + { .compatible = "mediatek,mt8195-dpi", + .data = (void *)MTK_DPI }, { .compatible = "mediatek,mt2701-dsi", .data = (void *)MTK_DSI }, { .compatible = "mediatek,mt8173-dsi",
Add support for the DPI block found in the MT8195 and MT8188 SoCs. Inside of the SoC, this block is directly connected to the HDMI IP. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> --- drivers/gpu/drm/mediatek/mtk_dpi.c | 24 ++++++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 6 ++++++ drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 ++ 3 files changed, 32 insertions(+)