diff mbox series

[v4,1/3] dt-bindings: pinctrl: mediatek: Add support for mt8196

Message ID 20250228011702.16493-2-ot_cathy.xu@mediatek.com (mailing list archive)
State New
Headers show
Series pinctrl: mediatek: Add pinctrl driver on mt8196 | expand

Commit Message

Cathy Xu (许华婷) Feb. 28, 2025, 1:16 a.m. UTC
Add the new binding document for pinctrl on MediaTek mt8196.

Signed-off-by: Guodong Liu <guodong.liu@mediatek.com>
Signed-off-by: Cathy Xu <ot_cathy.xu@mediatek.com>
---
 .../pinctrl/mediatek,mt8196-pinctrl.yaml      | 241 ++++++++++++++++++
 1 file changed, 241 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt8196-pinctrl.yaml

Comments

Rob Herring (Arm) Feb. 28, 2025, 2:26 a.m. UTC | #1
On Fri, 28 Feb 2025 09:16:25 +0800, Cathy Xu wrote:
> Add the new binding document for pinctrl on MediaTek mt8196.
> 
> Signed-off-by: Guodong Liu <guodong.liu@mediatek.com>
> Signed-off-by: Cathy Xu <ot_cathy.xu@mediatek.com>
> ---
>  .../pinctrl/mediatek,mt8196-pinctrl.yaml      | 241 ++++++++++++++++++
>  1 file changed, 241 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt8196-pinctrl.yaml
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:

dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/pinctrl/mediatek,mt8196-pinctrl.example.dts:24:18: fatal error: ../../../../arch/arm64/boot/dts/mediatek/mt8196-pinfunc.h: No such file or directory
   24 |         #include "../../../../arch/arm64/boot/dts/mediatek/mt8196-pinfunc.h"
      |                  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[2]: *** [scripts/Makefile.dtbs:131: Documentation/devicetree/bindings/pinctrl/mediatek,mt8196-pinctrl.example.dtb] Error 1
make[2]: *** Waiting for unfinished jobs....
make[1]: *** [/builds/robherring/dt-review-ci/linux/Makefile:1511: dt_binding_check] Error 2
make: *** [Makefile:251: __sub-make] Error 2

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20250228011702.16493-2-ot_cathy.xu@mediatek.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
Cathy Xu (许华婷) Feb. 28, 2025, 3:11 a.m. UTC | #2
On Thu, 2025-02-27 at 20:26 -0600, Rob Herring (Arm) wrote:
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> 
> 
> On Fri, 28 Feb 2025 09:16:25 +0800, Cathy Xu wrote:
> > Add the new binding document for pinctrl on MediaTek mt8196.
> > 
> > Signed-off-by: Guodong Liu <guodong.liu@mediatek.com>
> > Signed-off-by: Cathy Xu <ot_cathy.xu@mediatek.com>
> > ---
> >  .../pinctrl/mediatek,mt8196-pinctrl.yaml      | 241
> > ++++++++++++++++++
> >  1 file changed, 241 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/pinctrl/mediatek,mt8196-
> > pinctrl.yaml
> > 
> 
> My bot found errors running 'make dt_binding_check' on your patch:

  Sorry, this patch depond on another patch:
  
https://patchwork.kernel.org/project/linux-mediatek/patch/20250228011702.16493-3-ot_cathy.xu@mediatek.com/
  In this case, does the dt-binding still need go first? If so, I 
will include the dependency information in the commit message of 
the next version. Thank you~

> 
> yamllint warnings/errors:
> 
> dtschema/dtc warnings/errors:
> Documentation/devicetree/bindings/pinctrl/mediatek,mt8196-
> pinctrl.example.dts:24:18: fatal error:
> ../../../../arch/arm64/boot/dts/mediatek/mt8196-pinfunc.h: No such
> file or directory
>    24 |         #include
> "../../../../arch/arm64/boot/dts/mediatek/mt8196-pinfunc.h"
>       |                  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> ~~~~~~~~~~~~~~~
> compilation terminated.
> make[2]: *** [scripts/Makefile.dtbs:131:
> Documentation/devicetree/bindings/pinctrl/mediatek,mt8196-
> pinctrl.example.dtb] Error 1
> make[2]: *** Waiting for unfinished jobs....
> make[1]: *** [/builds/robherring/dt-review-ci/linux/Makefile:1511:
> dt_binding_check] Error 2
> make: *** [Makefile:251: __sub-make] Error 2
> 
> doc reference errors (make refcheckdocs):
> 
> See 
> https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20250228011702.16493-2-ot_cathy.xu@mediatek.com
> 
> The base for the series is generally the latest rc1. A different
> dependency
> should be noted in *this* patch.
> 
> If you already ran 'make dt_binding_check' and didn't see the above
> error(s), then make sure 'yamllint' is installed and dt-schema is up
> to
> date:
> 
> pip3 install dtschema --upgrade
> 
> Please check and re-submit after running the above command yourself.
> Note
> that DT_SCHEMA_FILES can be set to your schema file to speed up
> checking
> your schema. However, it must be unset to test all examples with your
> schema.
>
Krzysztof Kozlowski Feb. 28, 2025, 7:16 a.m. UTC | #3
On Fri, Feb 28, 2025 at 03:11:41AM +0000, Cathy Xu (许华婷) wrote:
> On Thu, 2025-02-27 at 20:26 -0600, Rob Herring (Arm) wrote:
> > External email : Please do not click links or open attachments until
> > you have verified the sender or the content.
> > 
> > 
> > On Fri, 28 Feb 2025 09:16:25 +0800, Cathy Xu wrote:
> > > Add the new binding document for pinctrl on MediaTek mt8196.
> > > 
> > > Signed-off-by: Guodong Liu <guodong.liu@mediatek.com>
> > > Signed-off-by: Cathy Xu <ot_cathy.xu@mediatek.com>
> > > ---
> > >  .../pinctrl/mediatek,mt8196-pinctrl.yaml      | 241
> > > ++++++++++++++++++
> > >  1 file changed, 241 insertions(+)
> > >  create mode 100644
> > > Documentation/devicetree/bindings/pinctrl/mediatek,mt8196-
> > > pinctrl.yaml
> > > 
> > 
> > My bot found errors running 'make dt_binding_check' on your patch:
> 
>   Sorry, this patch depond on another patch:
>   
> https://patchwork.kernel.org/project/linux-mediatek/patch/20250228011702.16493-3-ot_cathy.xu@mediatek.com/
>   In this case, does the dt-binding still need go first? If so, I 

This means your series are non-bisectable but even re-ordering will nto
fix it. You understand you target different trees?

> will include the dependency information in the commit message of 
> the next version. Thank you~

No, decouple from dependencies.

Best regards,
Krzysztof
Cathy Xu (许华婷) Feb. 28, 2025, 8:54 a.m. UTC | #4
On Fri, 2025-02-28 at 08:16 +0100, Krzysztof Kozlowski wrote:
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> 
> 
> On Fri, Feb 28, 2025 at 03:11:41AM +0000, Cathy Xu (许华婷) wrote:
> > On Thu, 2025-02-27 at 20:26 -0600, Rob Herring (Arm) wrote:
> > > External email : Please do not click links or open attachments
> > > until
> > > you have verified the sender or the content.
> > > 
> > > 
> > > On Fri, 28 Feb 2025 09:16:25 +0800, Cathy Xu wrote:
> > > > Add the new binding document for pinctrl on MediaTek mt8196.
> > > > 
> > > > Signed-off-by: Guodong Liu <guodong.liu@mediatek.com>
> > > > Signed-off-by: Cathy Xu <ot_cathy.xu@mediatek.com>
> > > > ---
> > > >  .../pinctrl/mediatek,mt8196-pinctrl.yaml      | 241
> > > > ++++++++++++++++++
> > > >  1 file changed, 241 insertions(+)
> > > >  create mode 100644
> > > > Documentation/devicetree/bindings/pinctrl/mediatek,mt8196-
> > > > pinctrl.yaml
> > > > 
> > > 
> > > My bot found errors running 'make dt_binding_check' on your
> > > patch:
> > 
> >   Sorry, this patch depond on another patch:
> > 
> > 
https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20250228011702.16493-3-ot_cathy.xu@mediatek.com/__;!!CTRNKA9wMg0ARbw!j88RnczPxn7KsWsGgrJFx94TWj7AAkm1F8MLC1hioQUb-zITN_P3YFH3bBgmdo6-2CNyqNqtDPHlLdQkPw$
> >   In this case, does the dt-binding still need go first? If so, I
> 
> This means your series are non-bisectable but even re-ordering will
> nto
> fix it. You understand you target different trees?

  Understand.

> 
> > will include the dependency information in the commit message of
> > the next version. Thank you~
> 
> No, decouple from dependencies.

  Ok, it will be fixed in next version.

> 
> Best regards,
> Krzysztof
>
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8196-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8196-pinctrl.yaml
new file mode 100644
index 000000000000..3100455c3c9d
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8196-pinctrl.yaml
@@ -0,0 +1,241 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8196-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek MT8196 Pin Controller
+
+maintainers:
+  - Lei Xue <lei.xue@mediatek.com>
+  - Cathy Xu <ot_cathy.xu@mediatek.com>
+
+description:
+  The MediaTek's MT8196 Pin controller is used to control SoC pins.
+
+properties:
+  compatible:
+    const: mediatek,mt8196-pinctrl
+
+  gpio-controller: true
+
+  '#gpio-cells':
+    description:
+      Number of cells in GPIO specifier, should be two. The first cell is the
+      pin number, the second cell is used to specify optional parameters which
+      are defined in <dt-bindings/gpio/gpio.h>.
+    const: 2
+
+  gpio-ranges:
+    maxItems: 1
+
+  gpio-line-names: true
+
+  reg:
+    items:
+      - description: gpio registers base address
+      - description: rt group io configuration registers base address
+      - description: rm1 group io configuration registers base address
+      - description: rm2 group io configuration registers base address
+      - description: rb group io configuration registers base address
+      - description: bm1 group io configuration registers base address
+      - description: bm2 group io configuration registers base address
+      - description: bm3 group io configuration registers base address
+      - description: lt group io configuration registers base address
+      - description: lm1 group io configuration registers base address
+      - description: lm2 group io configuration registers base address
+      - description: lb1 group io configuration registers base address
+      - description: lb2 group io configuration registers base address
+      - description: tm1 group io configuration registers base address
+      - description: tm2 group io configuration registers base address
+      - description: tm3 group io configuration registers base address
+
+  reg-names:
+    items:
+      - const: iocfg0
+      - const: iocfg_rt
+      - const: iocfg_rm1
+      - const: iocfg_rm2
+      - const: iocfg_rb
+      - const: iocfg_bm1
+      - const: iocfg_bm2
+      - const: iocfg_bm3
+      - const: iocfg_lt
+      - const: iocfg_lm1
+      - const: iocfg_lm2
+      - const: iocfg_lb1
+      - const: iocfg_lb2
+      - const: iocfg_tm1
+      - const: iocfg_tm2
+      - const: iocfg_tm3
+
+  interrupt-controller: true
+
+  '#interrupt-cells':
+    const: 2
+
+  interrupts:
+    description: The interrupt outputs to sysirq.
+    maxItems: 1
+
+# PIN CONFIGURATION NODES
+patternProperties:
+  '-pins$':
+    type: object
+    additionalProperties: false
+
+    patternProperties:
+      '^pins':
+        type: object
+        $ref: /schemas/pinctrl/pincfg-node.yaml
+        additionalProperties: false
+        description:
+          A pinctrl node should contain at least one subnode representing the
+          pinctrl groups available on the machine. Each subnode will list the
+          pins it needs, and how they should be configured, with regard to muxer
+          configuration, pullups, drive strength, input enable/disable and input
+          schmitt.
+
+        properties:
+          pinmux:
+            description:
+              Integer array, represents gpio pin number and mux setting.
+              Supported pin number and mux varies for different SoCs, and are
+              defined as macros in arch/arm64/boot/dts/mediatek/mt8196-pinfunc.h
+              directly, for this SoC.
+
+          drive-strength:
+            enum: [2, 4, 6, 8, 10, 12, 14, 16]
+
+          bias-pull-down:
+            oneOf:
+              - type: boolean
+              - enum: [100, 101, 102, 103]
+                description: mt8196 pull down PUPD/R0/R1 type define value.
+              - enum: [75000, 5000]
+                description: mt8196 pull down RSEL type si unit value(ohm).
+            description: |
+              For pull down type is normal, it doesn't need add R1R0 define
+              and resistance value.
+              For pull down type is PUPD/R0/R1 type, it can add R1R0 define to
+              set different resistance. It can support "MTK_PUPD_SET_R1R0_00" &
+              "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" &
+              "MTK_PUPD_SET_R1R0_11" define in mt8196.
+              For pull down type is PD/RSEL, it can add resistance value(ohm)
+              to set different resistance by identifying property
+              "mediatek,rsel-resistance-in-si-unit". It can support resistance
+              value(ohm) "75000" & "5000" in mt8196.
+
+          bias-pull-up:
+            oneOf:
+              - type: boolean
+              - enum: [100, 101, 102, 103]
+                description: mt8196 pull up PUPD/R0/R1 type define value.
+              - enum: [1000, 1500, 2000, 3000, 4000, 5000, 75000]
+                description: mt8196 pull up RSEL type si unit value(ohm).
+            description: |
+              For pull up type is normal, it don't need add R1R0 define
+              and resistance value.
+              For pull up type is PUPD/R0/R1 type, it can add R1R0 define to
+              set different resistance. It can support "MTK_PUPD_SET_R1R0_00" &
+              "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" &
+              "MTK_PUPD_SET_R1R0_11" define in mt8196.
+              For pull up type is PU/RSEL, it can add resistance value(ohm)
+              to set different resistance by identifying property
+              "mediatek,rsel-resistance-in-si-unit". It can support resistance
+              value(ohm) "1000" & "1500" & "2000" & "3000" & "4000" & "5000" &
+              "75000" in mt8196.
+
+          bias-disable: true
+
+          output-high: true
+
+          output-low: true
+
+          input-enable: true
+
+          input-disable: true
+
+          input-schmitt-enable: true
+
+          input-schmitt-disable: true
+
+        required:
+          - pinmux
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - interrupt-controller
+  - '#interrupt-cells'
+  - gpio-controller
+  - '#gpio-cells'
+  - gpio-ranges
+
+additionalProperties: false
+
+examples:
+  - |
+    #include "../../../../arch/arm64/boot/dts/mediatek/mt8196-pinfunc.h"
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    pio: pinctrl@10005000 {
+        compatible = "mediatek,mt8196-pinctrl";
+        reg = <0x1002d000 0x1000>,
+              <0x12000000 0x1000>,
+              <0x12020000 0x1000>,
+              <0x12040000 0x1000>,
+              <0x12060000 0x1000>,
+              <0x12820000 0x1000>,
+              <0x12840000 0x1000>,
+              <0x12860000 0x1000>,
+              <0x13000000 0x1000>,
+              <0x13020000 0x1000>,
+              <0x13040000 0x1000>,
+              <0x130f0000 0x1000>,
+              <0x13110000 0x1000>,
+              <0x13800000 0x1000>,
+              <0x13820000 0x1000>,
+              <0x13860000 0x1000>;
+        reg-names = "iocfg0", "iocfg_rt",
+                    "iocfg_rm1", "iocfg_rm2", "iocfg_rb",
+                    "iocfg_bm1", "iocfg_bm2", "iocfg_bm3",
+                    "iocfg_lt", "iocfg_lm1", "iocfg_lm2",
+                    "iocfg_lb1", "iocfg_lb2", "iocfg_tm1",
+                    "iocfg_tm2", "iocfg_tm3";
+        gpio-controller;
+        #gpio-cells = <2>;
+        gpio-ranges = <&pio 0 0 271>;
+        interrupt-controller;
+        interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH 0>;
+        #interrupt-cells = <2>;
+
+        pio-pins {
+            pins {
+                pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
+                output-low;
+            };
+        };
+
+        spi0-pins {
+            pins-spi {
+                pinmux = <PINMUX_GPIO110__FUNC_SPI1_CLK>,
+                         <PINMUX_GPIO111__FUNC_SPI1_CSB>,
+                         <PINMUX_GPIO112__FUNC_SPI1_MO>;
+                drive-strength = <6>;
+            };
+            pins-spi-mi {
+                pinmux = <PINMUX_GPIO113__FUNC_SPI1_MI>;
+                bias-pull-down;
+            };
+        };
+
+        i2c0-pins {
+            pins {
+                pinmux = <PINMUX_GPIO99__FUNC_SCL0>,
+                         <PINMUX_GPIO100__FUNC_SDA0>;
+                bias-disable;
+            };
+        };
+    };