diff mbox series

[v3,net-next,1/8] arm64: dts: mediatek: mt7986: add support for RX Wireless Ethernet Dispatch

Message ID 4bd5f6626174ac042c0e9b9f2ffff40c3c72b88a.1667466887.git.lorenzo@kernel.org (mailing list archive)
State New, archived
Headers show
Series introduce WED RX support to MT7986 SoC | expand

Commit Message

Lorenzo Bianconi Nov. 3, 2022, 9:28 a.m. UTC 
Similar to TX Wireless Ethernet Dispatch, introduce RX Wireless Ethernet
Dispatch to offload traffic received by the wlan interface to lan/wan
one.

Co-developed-by: Sujuan Chen <sujuan.chen@mediatek.com>
Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
 arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 75 +++++++++++++++++++++++
 1 file changed, 75 insertions(+)

Comments

AngeloGioacchino Del Regno Nov. 3, 2022, 2:13 p.m. UTC | #1 
Il 03/11/22 10:28, Lorenzo Bianconi ha scritto:
> Similar to TX Wireless Ethernet Dispatch, introduce RX Wireless Ethernet
> Dispatch to offload traffic received by the wlan interface to lan/wan
> one.
> 
> Co-developed-by: Sujuan Chen <sujuan.chen@mediatek.com>
> Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>

Hello Lorenzo,
thanks for the patch! However, there's something to improve...

> ---
>   arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 75 +++++++++++++++++++++++
>   1 file changed, 75 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
> index 72e0d9722e07..b0a593c6020e 100644
> --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi

..snip..

> @@ -226,6 +252,12 @@ ethsys: syscon@15000000 {
>   			 reg = <0 0x15000000 0 0x1000>;
>   			 #clock-cells = <1>;
>   			 #reset-cells = <1>;
> +
> +			ethsysrst: reset-controller {

That's not right. It works, yes, but your ethsys rightfully declares #reset-cells,
because it is supposed to also be a reset controller (even though I don't see any
reset controller registering action in clk-mt7986-eth.c).

Please document the ethernet reset in the appropriate dt-bindings header and
register the reset controller in clk-mt7986-eth.c.

Finally, you won't need any "ti,syscon-reset" node, and resets will look like

	resets = <&ethsys MT7986_ETHSYS_SOMETHING_SWRST>;

If you need any hint about how to do that, please check clk-mt8195-infra_ao.c.

Regards,
Angelo
Lorenzo Bianconi Nov. 3, 2022, 5:58 p.m. UTC | #2 
> Il 03/11/22 10:28, Lorenzo Bianconi ha scritto:
> > Similar to TX Wireless Ethernet Dispatch, introduce RX Wireless Ethernet
> > Dispatch to offload traffic received by the wlan interface to lan/wan
> > one.
> > 
> > Co-developed-by: Sujuan Chen <sujuan.chen@mediatek.com>
> > Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
> > Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
> 
> Hello Lorenzo,
> thanks for the patch! However, there's something to improve...
> 
> > ---
> >   arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 75 +++++++++++++++++++++++
> >   1 file changed, 75 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
> > index 72e0d9722e07..b0a593c6020e 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
> 
> ..snip..
> 
> > @@ -226,6 +252,12 @@ ethsys: syscon@15000000 {
> >   			 reg = <0 0x15000000 0 0x1000>;
> >   			 #clock-cells = <1>;
> >   			 #reset-cells = <1>;
> > +
> > +			ethsysrst: reset-controller {
> 
> That's not right. It works, yes, but your ethsys rightfully declares #reset-cells,
> because it is supposed to also be a reset controller (even though I don't see any
> reset controller registering action in clk-mt7986-eth.c).
> 
> Please document the ethernet reset in the appropriate dt-bindings header and
> register the reset controller in clk-mt7986-eth.c.
> 
> Finally, you won't need any "ti,syscon-reset" node, and resets will look like
> 
> 	resets = <&ethsys MT7986_ETHSYS_SOMETHING_SWRST>;
> 
> If you need any hint about how to do that, please check clk-mt8195-infra_ao.c.

Hi Angelo,

Thx for the review. This is not strictly related to the wed rx support added in this
series, anyway I will look into it in the next revision.

Regards,
Lorenzo

> 
> Regards,
> Angelo
>
Lorenzo Bianconi Nov. 4, 2022, 9:05 a.m. UTC | #3 
> Il 03/11/22 10:28, Lorenzo Bianconi ha scritto:
> > Similar to TX Wireless Ethernet Dispatch, introduce RX Wireless Ethernet
> > Dispatch to offload traffic received by the wlan interface to lan/wan
> > one.
> > 
> > Co-developed-by: Sujuan Chen <sujuan.chen@mediatek.com>
> > Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
> > Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
> 
> Hello Lorenzo,

Hi Angelo,

> thanks for the patch! However, there's something to improve...
> 
> > ---
> >   arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 75 +++++++++++++++++++++++
> >   1 file changed, 75 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
> > index 72e0d9722e07..b0a593c6020e 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
> 
> ..snip..
> 
> > @@ -226,6 +252,12 @@ ethsys: syscon@15000000 {
> >   			 reg = <0 0x15000000 0 0x1000>;
> >   			 #clock-cells = <1>;
> >   			 #reset-cells = <1>;
> > +
> > +			ethsysrst: reset-controller {
> 
> That's not right. It works, yes, but your ethsys rightfully declares #reset-cells,
> because it is supposed to also be a reset controller (even though I don't see any
> reset controller registering action in clk-mt7986-eth.c).
> 
> Please document the ethernet reset in the appropriate dt-bindings header and
> register the reset controller in clk-mt7986-eth.c.
> 
> Finally, you won't need any "ti,syscon-reset" node, and resets will look like
> 
> 	resets = <&ethsys MT7986_ETHSYS_SOMETHING_SWRST>;
> 
> If you need any hint about how to do that, please check clk-mt8195-infra_ao.c.

reviewing the code I think we do not have any mt7986-eth reset line consumer at the
moment, since:
- mtk_eth_soc driver rely on syscon for resetting the chip writing directly in the register
  in ethsys_reset()
- we do not rely on reset api in wed wo code.

I think we can just drop reset support in ethsys/wo-dlm nodes at the moment (since it
is not used in this series) and convert the driver to reset api as soon as
we have proper support in clk-mt7986-eth.c (AFAIU sam will work on it).

Regards,
Lorenzo

> 
> Regards,
> Angelo
>
AngeloGioacchino Del Regno Nov. 4, 2022, 9:10 a.m. UTC | #4 
Il 04/11/22 10:05, Lorenzo Bianconi ha scritto:
>> Il 03/11/22 10:28, Lorenzo Bianconi ha scritto:
>>> Similar to TX Wireless Ethernet Dispatch, introduce RX Wireless Ethernet
>>> Dispatch to offload traffic received by the wlan interface to lan/wan
>>> one.
>>>
>>> Co-developed-by: Sujuan Chen <sujuan.chen@mediatek.com>
>>> Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
>>> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
>>
>> Hello Lorenzo,
> 
> Hi Angelo,
> 
>> thanks for the patch! However, there's something to improve...
>>
>>> ---
>>>    arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 75 +++++++++++++++++++++++
>>>    1 file changed, 75 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
>>> index 72e0d9722e07..b0a593c6020e 100644
>>> --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
>>> +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
>>
>> ..snip..
>>
>>> @@ -226,6 +252,12 @@ ethsys: syscon@15000000 {
>>>    			 reg = <0 0x15000000 0 0x1000>;
>>>    			 #clock-cells = <1>;
>>>    			 #reset-cells = <1>;
>>> +
>>> +			ethsysrst: reset-controller {
>>
>> That's not right. It works, yes, but your ethsys rightfully declares #reset-cells,
>> because it is supposed to also be a reset controller (even though I don't see any
>> reset controller registering action in clk-mt7986-eth.c).
>>
>> Please document the ethernet reset in the appropriate dt-bindings header and
>> register the reset controller in clk-mt7986-eth.c.
>>
>> Finally, you won't need any "ti,syscon-reset" node, and resets will look like
>>
>> 	resets = <&ethsys MT7986_ETHSYS_SOMETHING_SWRST>;
>>
>> If you need any hint about how to do that, please check clk-mt8195-infra_ao.c.
> 
> reviewing the code I think we do not have any mt7986-eth reset line consumer at the
> moment, since:
> - mtk_eth_soc driver rely on syscon for resetting the chip writing directly in the register
>    in ethsys_reset()

Ouch :-)

> - we do not rely on reset api in wed wo code.
> 
> I think we can just drop reset support in ethsys/wo-dlm nodes at the moment (since it
> is not used in this series) and convert the driver to reset api as soon as
> we have proper support in clk-mt7986-eth.c (AFAIU sam will work on it).
> 

If you don't need to add resets to devicetree... then I guess dropping it is ok,
let's go with that.

Regards,
Angelo
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
index 72e0d9722e07..b0a593c6020e 100644
--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
@@ -8,6 +8,7 @@ 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/mt7986-clk.h>
 #include <dt-bindings/reset/mt7986-resets.h>
+#include <dt-bindings/reset/ti-syscon.h>
 
 / {
 	interrupt-parent = <&gic>;
@@ -76,6 +77,31 @@  wmcpu_emi: wmcpu-reserved@4fc00000 {
 			no-map;
 			reg = <0 0x4fc00000 0 0x00100000>;
 		};
+
+		wo_emi0: wo-emi@4fd00000 {
+			reg = <0 0x4fd00000 0 0x40000>;
+			no-map;
+		};
+
+		wo_emi1: wo-emi@4fd40000 {
+			reg = <0 0x4fd40000 0 0x40000>;
+			no-map;
+		};
+
+		wo_ilm0: wo-ilm@151e0000 {
+			reg = <0 0x151e0000 0 0x8000>;
+			no-map;
+		};
+
+		wo_ilm1: wo-ilm@151f0000 {
+			reg = <0 0x151f0000 0 0x8000>;
+			no-map;
+		};
+
+		wo_data: wo-data@4fd80000 {
+			reg = <0 0x4fd80000 0 0x240000>;
+			no-map;
+		};
 	};
 
 	timer {
@@ -226,6 +252,12 @@  ethsys: syscon@15000000 {
 			 reg = <0 0x15000000 0 0x1000>;
 			 #clock-cells = <1>;
 			 #reset-cells = <1>;
+
+			ethsysrst: reset-controller {
+				compatible = "ti,syscon-reset";
+				#reset-cells = <1>;
+				ti,reset-bits = <0x34 4 0x34 4 0x34 4 (ASSERT_SET | DEASSERT_CLEAR | STATUS_SET)>;
+			};
 		};
 
 		wed_pcie: wed-pcie@10003000 {
@@ -240,6 +272,11 @@  wed0: wed@15010000 {
 			reg = <0 0x15010000 0 0x1000>;
 			interrupt-parent = <&gic>;
 			interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+			memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_data>;
+			memory-region-names = "wo-emi", "wo-ilm", "wo-data";
+			mediatek,wo-ccif = <&wo_ccif0>;
+			mediatek,wo-boot = <&wo_boot>;
+			mediatek,wo-dlm = <&wo_dlm0>;
 		};
 
 		wed1: wed@15011000 {
@@ -248,6 +285,44 @@  wed1: wed@15011000 {
 			reg = <0 0x15011000 0 0x1000>;
 			interrupt-parent = <&gic>;
 			interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
+			memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_data>;
+			memory-region-names = "wo-emi", "wo-ilm", "wo-data";
+			mediatek,wo-ccif = <&wo_ccif1>;
+			mediatek,wo-boot = <&wo_boot>;
+			mediatek,wo-dlm = <&wo_dlm1>;
+		};
+
+		wo_ccif0: syscon@151a5000 {
+			compatible = "mediatek,mt7986-wo-ccif", "syscon";
+			reg = <0 0x151a5000 0 0x1000>;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		wo_ccif1: syscon@151ad000 {
+			compatible = "mediatek,mt7986-wo-ccif", "syscon";
+			reg = <0 0x151ad000 0 0x1000>;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		wo_dlm0: wo-dlm@151e8000 {
+			compatible = "mediatek,mt7986-wo-dlm";
+			reg = <0 0x151e8000 0 0x2000>;
+			resets = <&ethsysrst 0>;
+			reset-names = "wocpu_rst";
+		};
+
+		wo_dlm1: wo-dlm@151f8000 {
+			compatible = "mediatek,mt7986-wo-dlm";
+			reg = <0 0x151f8000 0 0x2000>;
+			resets = <&ethsysrst 0>;
+			reset-names = "wocpu_rst";
+		};
+
+		wo_boot: syscon@15194000 {
+			compatible = "mediatek,mt7986-wo-boot", "syscon";
+			reg = <0 0x15194000 0 0x1000>;
 		};
 
 		eth: ethernet@15100000 {