| Message ID | fc157139e6b7f8dfb6430ac7191ba754027705e8.1708221995.git.daniel@makrotopia.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | clk: mediatek: mt7981-topckgen: flag SGM_REG_SEL as critical | expand |
Il 18/02/24 04:11, Daniel Golle ha scritto: > Without the SGM_REG_SEL clock enabled the cpu freezes if trying to > access registers used by MT7981 clock drivers itself. > Mark SGM_REG_SEL as critical to make sure it is always enabled to > prevent freezes on boot even if the Ethernet driver which prepares > and enables the clock is not loaded or probed at a later point. > > Fixes: 813c3b53b55b ("clk: mediatek: add MT7981 clock support") > Signed-off-by: Daniel Golle <daniel@makrotopia.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Quoting Daniel Golle (2024-02-17 19:11:15) > Without the SGM_REG_SEL clock enabled the cpu freezes if trying to > access registers used by MT7981 clock drivers itself. > Mark SGM_REG_SEL as critical to make sure it is always enabled to > prevent freezes on boot even if the Ethernet driver which prepares > and enables the clock is not loaded or probed at a later point. > > Fixes: 813c3b53b55b ("clk: mediatek: add MT7981 clock support") > Signed-off-by: Daniel Golle <daniel@makrotopia.org> > --- Applied to clk-next
diff --git a/drivers/clk/mediatek/clk-mt7981-topckgen.c b/drivers/clk/mediatek/clk-mt7981-topckgen.c index 682f4ca9e89ad..493aa11d3a175 100644 --- a/drivers/clk/mediatek/clk-mt7981-topckgen.c +++ b/drivers/clk/mediatek/clk-mt7981-topckgen.c @@ -357,8 +357,9 @@ static const struct mtk_mux top_muxes[] = { MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel", sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15, 0x1C0, 21), - MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents, - 0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22), + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents, + 0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP97B_SEL, "eip97b_sel", eip97b_parents, 0x050, 0x054, 0x058, 24, 3, 31, 0x1C0, 23), /* CLK_CFG_6 */
Without the SGM_REG_SEL clock enabled the cpu freezes if trying to access registers used by MT7981 clock drivers itself. Mark SGM_REG_SEL as critical to make sure it is always enabled to prevent freezes on boot even if the Ethernet driver which prepares and enables the clock is not loaded or probed at a later point. Fixes: 813c3b53b55b ("clk: mediatek: add MT7981 clock support") Signed-off-by: Daniel Golle <daniel@makrotopia.org> --- drivers/clk/mediatek/clk-mt7981-topckgen.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)