[0/1] clk: jz4725b: fix mmc0 clock gating

Message

Siarhei Volkau Feb. 4, 2022, 5:26 a.m. UTC

The mmc0 clock gate bit was mistakenly assigned to "i2s" clock.
You can find that the same bit is assigned to "mmc0" too.
It leads to mmc0 hang for a long time after any sound activity
also it  prevented PM_SLEEP to work properly.
I guess it was introduced by copy-paste from jz4740 driver
where it is really controls I2S clock gate.

Siarhei Volkau (1):
  clk: jz4725b: fix mmc0 clock gating

 drivers/clk/ingenic/jz4725b-cgu.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

Comments

Paul Cercueil Feb. 4, 2022, 6:23 a.m. UTC | #1

Hi Siarhei,

Le ven., févr. 4 2022 at 08:26:40 +0300, Siarhei Volkau 
<[e-mail]> a écrit :
> The mmc0 clock gate bit was mistakenly assigned to "i2s" clock.
> You can find that the same bit is assigned to "mmc0" too.
> It leads to mmc0 hang for a long time after any sound activity
> also it  prevented PM_SLEEP to work properly.
> I guess it was introduced by copy-paste from jz4740 driver
> where it is really controls I2S clock gate.

This is useful information, please use the same text in the commit 
message.

However... My JZ4725B programming manual does say that the MMC0 clock 
is gated with bit 6, and the I2S clock has no gating bit.

Where did you find this info?

Cheers,
-Paul

> 
> Siarhei Volkau (1):
>   clk: jz4725b: fix mmc0 clock gating
> 
>  drivers/clk/ingenic/jz4725b-cgu.c | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
> 
> --
> 2.35.1
>

Siarhei Volkau Feb. 4, 2022, 6:53 a.m. UTC | #2

пт, 4 февр. 2022 г. в 09:24, Paul Cercueil <[e-mail]>:
>
> Hi Siarhei,

Hi Paul,

> Le ven., févr. 4 2022 at 08:26:40 +0300, Siarhei Volkau
> <[e-mail]> a écrit :
> > The mmc0 clock gate bit was mistakenly assigned to "i2s" clock.
> > You can find that the same bit is assigned to "mmc0" too.
> > It leads to mmc0 hang for a long time after any sound activity
> > also it  prevented PM_SLEEP to work properly.
> > I guess it was introduced by copy-paste from jz4740 driver
> > where it is really controls I2S clock gate.
>
> This is useful information, please use the same text in the commit
> message.
Ok.
>
> However... My JZ4725B programming manual does say that the MMC0 clock
> is gated with bit 6, and the I2S clock has no gating bit.
>
> Where did you find this info?
My programming manual says exactly the same, but look at the clk
driver source - the bit 6
is used in both clock domains (i2s and mmc0). That's the patch intended to fix.
Background: I'm trying to port OpenDingux to a Ritmix RZX-27 device.
It uses mmc0 as main storage. That's where the problem arises - after
init.d/alsa-hack.sh
mmc0 hungs for ~5 minutes till sdmmc core does reset it.
>
> Cheers,
> -Paul
>
> >
> > Siarhei Volkau (1):
> >   clk: jz4725b: fix mmc0 clock gating
> >
> >  drivers/clk/ingenic/jz4725b-cgu.c | 3 +--
> >  1 file changed, 1 insertion(+), 2 deletions(-)
> >
> > --
> > 2.35.1
> >
>
>