[v3,0/2] irqchip/loongson-eiointc: Add multiple interrupt pin routing support

Message

Bibo Mao Dec. 13, 2024, 3:50 a.m. UTC

There are four times EIOINTC_REG_ISR register group access in eiointc irq
handler, in order to get all irq status about 256 interrupt vectors. It
causes four times VM-exits since eiointc register are software emulated,
here multiple interrupt pin routing is introduced and each 64 interrupt
vector is routed to one interrupt pin.

With this method, there will be only once EIOINTC_REG_ISR register
group acces in irq handler, it reduces VM-exits.

---
v2 ... v3:
  1. Update to latest kernel version and solve some confliction.
  2. Add strict check about multiple interrupt pin support, only the first
     eiointc device support this since intterrupt pin is limited. In order
     to support multiple eiointc driver in future if there is in future.

v1 ... v2:
  1. Add different route_info handler as eiointc interrupt handler
     parameter, so that irq handler can read corresponding ISR
  2. Call function set_csr_ecfg() to enable cpu interrupt pin in eiointc
     driver inside.
---
Bibo Mao (2):
  irqchip/loongson-eiointc: Route interrupt parsed from bios table
  irqchip/loongson-eiointc: Add multiple interrupt pin routing support

 drivers/irqchip/irq-loongson-eiointc.c | 96 +++++++++++++++++++++++---
 1 file changed, 88 insertions(+), 8 deletions(-)


base-commit: fac04efc5c793dccbd07e2d59af9f90b7fc0dca4