| Message ID | 1548517123-60058-4-git-send-email-zhouyanjie@zoho.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [1/4] Irqchip: Ingenic: Change interrupt handling form cascade to chained_irq. | expand |
On Sat, 26 Jan 2019 15:38:42 +0000, Zhou Yanjie <zhouyanjie@zoho.com> wrote: > > Add support for probing the irq-ingenic driver on the X1000 Soc. > X1000 is a 1.0GHz processor for IoT. It has MIPS32 XBurst RISC core > with double precision hardware float point unit. I don't think we need the marketing spiel, as none of the advertised target market, ISA or feature set of this SoC is relevant for this patch. Put it in the cover letter if you must. Instead, explaining that it behaves just like any of the other "2chip" Ingenic SoCs makes is much more relevant. > > Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com> > --- > drivers/irqchip/irq-ingenic.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/irqchip/irq-ingenic.c b/drivers/irqchip/irq-ingenic.c > index 69be219..0b643c7 100644 > --- a/drivers/irqchip/irq-ingenic.c > +++ b/drivers/irqchip/irq-ingenic.c > @@ -177,3 +177,4 @@ static int __init intc_2chip_of_init(struct device_node *node, > IRQCHIP_DECLARE(jz4770_intc, "ingenic,jz4770-intc", intc_2chip_of_init); > IRQCHIP_DECLARE(jz4775_intc, "ingenic,jz4775-intc", intc_2chip_of_init); > IRQCHIP_DECLARE(jz4780_intc, "ingenic,jz4780-intc", intc_2chip_of_init); > +IRQCHIP_DECLARE(x1000_intc, "ingenic,x1000-intc", intc_2chip_of_init); > -- > 2.7.4 > > Thanks, M.
Thanks for your suggestions, It will be deleted in the v2. On 2019年01月27日 18:14, Marc Zyngier wrote: > On Sat, 26 Jan 2019 15:38:42 +0000, > Zhou Yanjie <zhouyanjie@zoho.com> wrote: >> Add support for probing the irq-ingenic driver on the X1000 Soc. >> X1000 is a 1.0GHz processor for IoT. It has MIPS32 XBurst RISC core >> with double precision hardware float point unit. > I don't think we need the marketing spiel, as none of the advertised > target market, ISA or feature set of this SoC is relevant for this > patch. Put it in the cover letter if you must. > > Instead, explaining that it behaves just like any of the other "2chip" > Ingenic SoCs makes is much more relevant. > >> Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com> >> --- >> drivers/irqchip/irq-ingenic.c | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/drivers/irqchip/irq-ingenic.c b/drivers/irqchip/irq-ingenic.c >> index 69be219..0b643c7 100644 >> --- a/drivers/irqchip/irq-ingenic.c >> +++ b/drivers/irqchip/irq-ingenic.c >> @@ -177,3 +177,4 @@ static int __init intc_2chip_of_init(struct device_node *node, >> IRQCHIP_DECLARE(jz4770_intc, "ingenic,jz4770-intc", intc_2chip_of_init); >> IRQCHIP_DECLARE(jz4775_intc, "ingenic,jz4775-intc", intc_2chip_of_init); >> IRQCHIP_DECLARE(jz4780_intc, "ingenic,jz4780-intc", intc_2chip_of_init); >> +IRQCHIP_DECLARE(x1000_intc, "ingenic,x1000-intc", intc_2chip_of_init); >> -- >> 2.7.4 >> >> > Thanks, > > M. >
diff --git a/drivers/irqchip/irq-ingenic.c b/drivers/irqchip/irq-ingenic.c index 69be219..0b643c7 100644 --- a/drivers/irqchip/irq-ingenic.c +++ b/drivers/irqchip/irq-ingenic.c @@ -177,3 +177,4 @@ static int __init intc_2chip_of_init(struct device_node *node, IRQCHIP_DECLARE(jz4770_intc, "ingenic,jz4770-intc", intc_2chip_of_init); IRQCHIP_DECLARE(jz4775_intc, "ingenic,jz4775-intc", intc_2chip_of_init); IRQCHIP_DECLARE(jz4780_intc, "ingenic,jz4780-intc", intc_2chip_of_init); +IRQCHIP_DECLARE(x1000_intc, "ingenic,x1000-intc", intc_2chip_of_init);
Add support for probing the irq-ingenic driver on the X1000 Soc. X1000 is a 1.0GHz processor for IoT. It has MIPS32 XBurst RISC core with double precision hardware float point unit. Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com> --- drivers/irqchip/irq-ingenic.c | 1 + 1 file changed, 1 insertion(+)