| Message ID | 1548517123-60058-5-git-send-email-zhouyanjie@zoho.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [1/4] Irqchip: Ingenic: Change interrupt handling form cascade to chained_irq. | expand |
diff --git a/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt b/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt index d4373d0..fa69b3f 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt @@ -8,6 +8,7 @@ Required properties: ingenic,jz4770-intc ingenic,jz4775-intc ingenic,jz4780-intc + ingenic,x1000-intc - reg : Specifies base physical address and size of the registers. - interrupt-controller : Identifies the node as an interrupt controller - #interrupt-cells : Specifies the number of cells needed to encode an
Add support for probing the irq-ingenic driver on the X1000 Soc. X1000 is a 1.0GHz processor for IoT. It has MIPS32 XBurst RISC core with double precision hardware float point unit. Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com> --- Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt | 1 + 1 file changed, 1 insertion(+)