| Message ID | 1563192595-53546-8-git-send-email-zhouyanjie@zoho.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [v3,1/8] irqchip: Ingenic: Change interrupt handling form cascade to chained_irq. | expand |
diff --git a/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt b/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt index 4f91bda..a96e120 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt @@ -12,6 +12,7 @@ Required properties: ingenic,jz4780-intc ingenic,x1000-intc ingenic,x1000e-intc + ingenic,x1500-intc - reg : Specifies base physical address and size of the registers. - interrupt-controller : Identifies the node as an interrupt controller - #interrupt-cells : Specifies the number of cells needed to encode an
Add the interrupt-controller bindings for the X1500 Soc from Ingenic. Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com> --- Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt | 1 + 1 file changed, 1 insertion(+)