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[34.92.144.28]) by smtp.gmail.com with ESMTPSA id j17sm7223230pgk.66.2020.05.22.21.25.05 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 22 May 2020 21:25:06 -0700 (PDT) From: Huacai Chen To: Thomas Bogendoerfer Cc: linux-mips@vger.kernel.org, Fuxin Zhang , Zhangjin Wu , Huacai Chen , Jiaxun Yang , Huacai Chen Subject: [PATCH] MIPS: Tidy up CP0.Config6 bits definition Date: Sat, 23 May 2020 12:25:40 +0800 Message-Id: <1590207940-20157-1-git-send-email-chenhc@lemote.com> X-Mailer: git-send-email 2.7.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org CP0.Config6 is a Vendor-defined register whose bits definitions are different from one to another. Recently, Xuerui's Loongson-3 patch and Serge's P5600 patch make the definitions inconsistency and unclear. To make life easy, this patch tidy the definition up. Signed-off-by: Huacai Chen --- arch/mips/include/asm/mipsregs.h | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index fe6293f..e89eeb9 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -690,6 +690,12 @@ #define MIPS_CONF6_JRCD (_ULCAST_(1) << 0) /* MIPSr6 extensions enable */ #define MIPS_CONF6_R6 (_ULCAST_(1) << 2) +/* Loongson-3 internal timer bit */ +#define MIPS_CONF6_INTIMER (_ULCAST_(1) << 6) +/* Loongson-3 external timer bit */ +#define MIPS_CONF6_EXTIMER (_ULCAST_(1) << 7) +/* Loongson-3 SFB on/off bit */ +#define MIPS_CONF6_SFBEN (_ULCAST_(1) << 8) /* IFU Performance Control */ #define MIPS_CONF6_IFUPERFCTL (_ULCAST_(3) << 10) #define MIPS_CONF6_SYND (_ULCAST_(1) << 13) @@ -697,16 +703,16 @@ #define MIPS_CONF6_SPCD (_ULCAST_(1) << 14) /* proAptiv FTLB on/off bit */ #define MIPS_CONF6_FTLBEN (_ULCAST_(1) << 15) +/* Loongson-3's LL on exclusive cacheline */ +#define MIPS_CONF6_LLEXC (_ULCAST_(1) << 16) +/* Loongson-3's SC has a random delay */ +#define MIPS_CONF6_SCRAND (_ULCAST_(1) << 17) /* Disable load/store bonding */ #define MIPS_CONF6_DLSB (_ULCAST_(1) << 21) /* Loongson-3 FTLB on/off bit */ #define MIPS_CONF6_FTLBDIS (_ULCAST_(1) << 22) /* FTLB probability bits */ #define MIPS_CONF6_FTLBP_SHIFT (16) -/* Loongson-3 feature bits */ -#define MIPS_CONF6_LOONGSON_SCRAND (_ULCAST_(1) << 17) -#define MIPS_CONF6_LOONGSON_LLEXC (_ULCAST_(1) << 16) -#define MIPS_CONF6_LOONGSON_STFILL (_ULCAST_(1) << 8) #define MIPS_CONF7_WII (_ULCAST_(1) << 31)