| Message ID | 1599624552-17523-3-git-send-email-chenhc@lemote.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [1/3] MIPS: Loongson64: Increase NR_IRQS to 320 | expand |
在 2020/9/9 12:09, Huacai Chen 写道: > Reserve legacy LPC irqs (0~15) to avoid spurious interrupts. It doesn't make sense at all. How can you allocate IRQ without irqchip backing it? - Jiaxun > > Cc: stable@vger.kernel.org > Signed-off-by: Huacai Chen <chenhc@lemote.com> > --- > drivers/irqchip/irq-loongson-pch-pic.c | 19 ++++++++++++++++++- > 1 file changed, 18 insertions(+), 1 deletion(-) > > diff --git a/drivers/irqchip/irq-loongson-pch-pic.c b/drivers/irqchip/irq-loongson-pch-pic.c > index 9bf6b9a..9f6719c 100644 > --- a/drivers/irqchip/irq-loongson-pch-pic.c > +++ b/drivers/irqchip/irq-loongson-pch-pic.c > @@ -35,6 +35,7 @@ > > struct pch_pic { > void __iomem *base; > + struct irq_domain *lpc_domain; > struct irq_domain *pic_domain; > u32 ht_vec_base; > raw_spinlock_t pic_lock; > @@ -184,9 +185,9 @@ static void pch_pic_reset(struct pch_pic *priv) > static int pch_pic_of_init(struct device_node *node, > struct device_node *parent) > { > + int i, base, err; > struct pch_pic *priv; > struct irq_domain *parent_domain; > - int err; > > priv = kzalloc(sizeof(*priv), GFP_KERNEL); > if (!priv) > @@ -213,6 +214,22 @@ static int pch_pic_of_init(struct device_node *node, > goto iounmap_base; > } > > + base = irq_alloc_descs(-1, 0, NR_IRQS_LEGACY, 0); > + if (base < 0) { > + pr_err("Failed to allocate LPC IRQ numbers\n"); > + goto iounmap_base; > + } > + > + priv->lpc_domain = irq_domain_add_legacy(node, NR_IRQS_LEGACY, 0, 0, > + &irq_domain_simple_ops, NULL); > + if (!priv->lpc_domain) { > + pr_err("Failed to add irqdomain for LPC controller"); > + goto iounmap_base; > + } > + > + for (i = 0; i < NR_IRQS_LEGACY; i++) > + irq_set_chip_and_handler(i, &dummy_irq_chip, handle_simple_irq); > + > priv->pic_domain = irq_domain_create_hierarchy(parent_domain, 0, > PIC_COUNT, > of_node_to_fwnode(node),
Hi, Jiaxun, On Thu, Sep 10, 2020 at 8:52 AM Jiaxun Yang <jiaxun.yang@flygoat.com> wrote: > > > > 在 2020/9/9 12:09, Huacai Chen 写道: > > Reserve legacy LPC irqs (0~15) to avoid spurious interrupts. > > It doesn't make sense at all. > > How can you allocate IRQ without irqchip backing it? > > - Jiaxun As you know, this patch resolves the kdump problem, and 0~15 is really needed to reserve for LPC, right? Huacai > > > > > Cc: stable@vger.kernel.org > > Signed-off-by: Huacai Chen <chenhc@lemote.com> > > --- > > drivers/irqchip/irq-loongson-pch-pic.c | 19 ++++++++++++++++++- > > 1 file changed, 18 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/irqchip/irq-loongson-pch-pic.c b/drivers/irqchip/irq-loongson-pch-pic.c > > index 9bf6b9a..9f6719c 100644 > > --- a/drivers/irqchip/irq-loongson-pch-pic.c > > +++ b/drivers/irqchip/irq-loongson-pch-pic.c > > @@ -35,6 +35,7 @@ > > > > struct pch_pic { > > void __iomem *base; > > + struct irq_domain *lpc_domain; > > struct irq_domain *pic_domain; > > u32 ht_vec_base; > > raw_spinlock_t pic_lock; > > @@ -184,9 +185,9 @@ static void pch_pic_reset(struct pch_pic *priv) > > static int pch_pic_of_init(struct device_node *node, > > struct device_node *parent) > > { > > + int i, base, err; > > struct pch_pic *priv; > > struct irq_domain *parent_domain; > > - int err; > > > > priv = kzalloc(sizeof(*priv), GFP_KERNEL); > > if (!priv) > > @@ -213,6 +214,22 @@ static int pch_pic_of_init(struct device_node *node, > > goto iounmap_base; > > } > > > > + base = irq_alloc_descs(-1, 0, NR_IRQS_LEGACY, 0); > > + if (base < 0) { > > + pr_err("Failed to allocate LPC IRQ numbers\n"); > > + goto iounmap_base; > > + } > > + > > + priv->lpc_domain = irq_domain_add_legacy(node, NR_IRQS_LEGACY, 0, 0, > > + &irq_domain_simple_ops, NULL); > > + if (!priv->lpc_domain) { > > + pr_err("Failed to add irqdomain for LPC controller"); > > + goto iounmap_base; > > + } > > + > > + for (i = 0; i < NR_IRQS_LEGACY; i++) > > + irq_set_chip_and_handler(i, &dummy_irq_chip, handle_simple_irq); > > + > > priv->pic_domain = irq_domain_create_hierarchy(parent_domain, 0, > > PIC_COUNT, > > of_node_to_fwnode(node),
On 2020-09-09 05:09, Huacai Chen wrote: > Reserve legacy LPC irqs (0~15) to avoid spurious interrupts. How can they be spurious? Why are they enabled the first place? This looks like you are papering over a much bigger issue. M. > > Cc: stable@vger.kernel.org > Signed-off-by: Huacai Chen <chenhc@lemote.com> > --- > drivers/irqchip/irq-loongson-pch-pic.c | 19 ++++++++++++++++++- > 1 file changed, 18 insertions(+), 1 deletion(-) > > diff --git a/drivers/irqchip/irq-loongson-pch-pic.c > b/drivers/irqchip/irq-loongson-pch-pic.c > index 9bf6b9a..9f6719c 100644 > --- a/drivers/irqchip/irq-loongson-pch-pic.c > +++ b/drivers/irqchip/irq-loongson-pch-pic.c > @@ -35,6 +35,7 @@ > > struct pch_pic { > void __iomem *base; > + struct irq_domain *lpc_domain; > struct irq_domain *pic_domain; > u32 ht_vec_base; > raw_spinlock_t pic_lock; > @@ -184,9 +185,9 @@ static void pch_pic_reset(struct pch_pic *priv) > static int pch_pic_of_init(struct device_node *node, > struct device_node *parent) > { > + int i, base, err; > struct pch_pic *priv; > struct irq_domain *parent_domain; > - int err; > > priv = kzalloc(sizeof(*priv), GFP_KERNEL); > if (!priv) > @@ -213,6 +214,22 @@ static int pch_pic_of_init(struct device_node > *node, > goto iounmap_base; > } > > + base = irq_alloc_descs(-1, 0, NR_IRQS_LEGACY, 0); > + if (base < 0) { > + pr_err("Failed to allocate LPC IRQ numbers\n"); > + goto iounmap_base; > + } > + > + priv->lpc_domain = irq_domain_add_legacy(node, NR_IRQS_LEGACY, 0, 0, > + &irq_domain_simple_ops, NULL); > + if (!priv->lpc_domain) { > + pr_err("Failed to add irqdomain for LPC controller"); > + goto iounmap_base; > + } > + > + for (i = 0; i < NR_IRQS_LEGACY; i++) > + irq_set_chip_and_handler(i, &dummy_irq_chip, handle_simple_irq); > + > priv->pic_domain = irq_domain_create_hierarchy(parent_domain, 0, > PIC_COUNT, > of_node_to_fwnode(node),
Hi
[This is an automated email]
This commit has been processed because it contains a -stable tag.
The stable tag indicates that it's relevant for the following trees: all
The bot has tested the following trees: v5.8.7, v5.4.63, v4.19.143, v4.14.196, v4.9.235, v4.4.235.
v5.8.7: Build OK!
v5.4.63: Failed to apply! Possible dependencies:
4134b762eb13 ("ARM: exynos: Enable exynos-asv driver for ARCH_EXYNOS")
818e915fbac5 ("irqchip: Add Loongson HyperTransport Vector support")
a93f1d903fa3 ("irqchip: Add driver for Loongson-3 HyperTransport PIC controller")
b74416dba33b ("irqchip: Define EXYNOS_IRQ_COMBINER")
dbb152267908 ("irqchip: Add driver for Loongson I/O Local Interrupt Controller")
ef8c01eb64ca ("irqchip: Add Loongson PCH PIC controller")
v4.19.143: Failed to apply! Possible dependencies:
0145beed9d26 ("irqchip: davinci-aintc: move the driver to drivers/irqchip")
06a287161429 ("ARM: davinci: aintc: use the new config structure")
1fa70c7f4913 ("ARM: exynos: Enable exynos-chipid driver")
2b6a2e74f2bf ("ARM: davinci: aintc: use a common prefix for symbols in the driver")
2d242aa28892 ("ARM: davinci: aintc: drop GPL license boilerplate")
4134b762eb13 ("ARM: exynos: Enable exynos-asv driver for ARCH_EXYNOS")
74b0eac24259 ("ARM: davinci: aintc: use irq domain")
818e915fbac5 ("irqchip: Add Loongson HyperTransport Vector support")
a93f1d903fa3 ("irqchip: Add driver for Loongson-3 HyperTransport PIC controller")
a98ca73ee348 ("ARM: davinci: wrap HW interrupt numbers with a macro")
b74416dba33b ("irqchip: Define EXYNOS_IRQ_COMBINER")
d0064594f20a ("ARM: davinci: select GENERIC_IRQ_MULTI_HANDLER")
dbb152267908 ("irqchip: Add driver for Loongson I/O Local Interrupt Controller")
de4f82a245ce ("ARM: davinci: aintc: wrap davinci_irq_init() with a helper")
ef8c01eb64ca ("irqchip: Add Loongson PCH PIC controller")
fd0f4275864d ("ARM: davinci: aintc: use the new irqchip config structure in dm* SoCs")
v4.14.196: Failed to apply! Possible dependencies:
0149385537e6 ("irqchip: Place CONFIG_SIFIVE_PLIC into the menu")
1fa70c7f4913 ("ARM: exynos: Enable exynos-chipid driver")
215f4cc0fb20 ("irqchip/meson: Add support for gpio interrupt controller")
33c57c0d3c67 ("RISC-V: Add a basic defconfig")
4134b762eb13 ("ARM: exynos: Enable exynos-asv driver for ARCH_EXYNOS")
4235ff50cf98 ("irqchip/irq-goldfish-pic: Add Goldfish PIC driver")
4a632cec8884 ("RISC-V: Enable module support in defconfig")
67d2075ad695 ("dt-bindings: irqchip: Introduce TISCI Interrupt router bindings")
706cffc1b912 ("irqchip/exiu: Add support for Socionext Synquacer EXIU controller")
818e915fbac5 ("irqchip: Add Loongson HyperTransport Vector support")
8237f8bc4f6e ("irqchip: add a SiFive PLIC driver")
9f1463b86c13 ("irqchip/ti-sci-inta: Add support for Interrupt Aggregator driver")
a93f1d903fa3 ("irqchip: Add driver for Loongson-3 HyperTransport PIC controller")
abe45fd9f1b0 ("irqchip: Andestech Internal Vector Interrupt Controller driver")
accaf1fbfb5d ("dt-bindings: irqchip: Introduce TISCI Interrupt Aggregator bindings")
b74416dba33b ("irqchip: Define EXYNOS_IRQ_COMBINER")
c2ba80af4805 ("dt-bindings/goldfish-pic: Add device tree binding for Goldfish PIC driver")
c94fb639d546 ("irqchip: Add Kconfig menu")
ca1c4d653524 ("MAINTAINERS: Add entry for sound/soc/ti and update the OMAP audio support")
cd844b0715ce ("irqchip/ti-sci-intr: Add support for Interrupt Router driver")
dbb152267908 ("irqchip: Add driver for Loongson I/O Local Interrupt Controller")
ef8c01eb64ca ("irqchip: Add Loongson PCH PIC controller")
f55c73aef890 ("irqchip/pdc: Add PDC interrupt controller for QCOM SoCs")
v4.9.235: Failed to apply! Possible dependencies:
0464a53eba0a ("MIPS: Update Goldfish RTC driver maintainer email address")
1fa70c7f4913 ("ARM: exynos: Enable exynos-chipid driver")
215f4cc0fb20 ("irqchip/meson: Add support for gpio interrupt controller")
33c57c0d3c67 ("RISC-V: Add a basic defconfig")
4134b762eb13 ("ARM: exynos: Enable exynos-asv driver for ARCH_EXYNOS")
4235ff50cf98 ("irqchip/irq-goldfish-pic: Add Goldfish PIC driver")
4a632cec8884 ("RISC-V: Enable module support in defconfig")
5ed34d3a4387 ("irqchip: Add UniPhier AIDET irqchip driver")
706cffc1b912 ("irqchip/exiu: Add support for Socionext Synquacer EXIU controller")
7a08de1d8fd2 ("dt-bindings: Add device tree binding for Goldfish RTC driver")
818e915fbac5 ("irqchip: Add Loongson HyperTransport Vector support")
8237f8bc4f6e ("irqchip: add a SiFive PLIC driver")
a93f1d903fa3 ("irqchip: Add driver for Loongson-3 HyperTransport PIC controller")
b74416dba33b ("irqchip: Define EXYNOS_IRQ_COMBINER")
c2ba80af4805 ("dt-bindings/goldfish-pic: Add device tree binding for Goldfish PIC driver")
c94fb639d546 ("irqchip: Add Kconfig menu")
dbb152267908 ("irqchip: Add driver for Loongson I/O Local Interrupt Controller")
ef8c01eb64ca ("irqchip: Add Loongson PCH PIC controller")
f20cc9b00c7b ("irqchip/qcom: Add IRQ combiner driver")
f22d9cdcb5eb ("rtc: goldfish: Add RTC driver for Android emulator")
f48e699ddf70 ("irqchip/aspeed-i2c-ic: Add I2C IRQ controller for Aspeed")
f55c73aef890 ("irqchip/pdc: Add PDC interrupt controller for QCOM SoCs")
v4.4.235: Failed to apply! Possible dependencies:
19afc3d269fe ("irqchip: i8259: Allow platforms to override poll function")
1fa70c7f4913 ("ARM: exynos: Enable exynos-chipid driver")
3900d6a85e66 ("ARM: EXYNOS: Split up exynos5250 SoC specific PMU data")
4134b762eb13 ("ARM: exynos: Enable exynos-asv driver for ARCH_EXYNOS")
73d72ed8e98c ("ARM: EXYNOS: Split up exynos4 SoC specific PMU data")
818e915fbac5 ("irqchip: Add Loongson HyperTransport Vector support")
8438aef01d35 ("ARM: EXYNOS: Remove redundant code from regs-pmu.h")
a93f1d903fa3 ("irqchip: Add driver for Loongson-3 HyperTransport PIC controller")
b74416dba33b ("irqchip: Define EXYNOS_IRQ_COMBINER")
bfce552d0b10 ("drivers: soc: Add support for Exynos PMU driver")
c21100c94dfa ("ARM: EXYNOS: Split up exynos3250 SoC specific PMU data")
d3bafff78331 ("ARM: EXYNOS: Enable ARCH_SUPPORTS_BIG_ENDIAN explicitly")
dbb152267908 ("irqchip: Add driver for Loongson I/O Local Interrupt Controller")
e32465429490 ("ARM: use "depends on" for SoC configs instead of "if" after prompt")
ef8c01eb64ca ("irqchip: Add Loongson PCH PIC controller")
NOTE: The patch will not be queued to stable trees until it is upstream.
How should we proceed with this patch?
Hi, Sasha, On Fri, Sep 11, 2020 at 1:18 AM Sasha Levin <sashal@kernel.org> wrote: > > Hi > > [This is an automated email] > > This commit has been processed because it contains a -stable tag. > The stable tag indicates that it's relevant for the following trees: all > > The bot has tested the following trees: v5.8.7, v5.4.63, v4.19.143, v4.14.196, v4.9.235, v4.4.235. > > v5.8.7: Build OK! > v5.4.63: Failed to apply! Possible dependencies: > 4134b762eb13 ("ARM: exynos: Enable exynos-asv driver for ARCH_EXYNOS") > 818e915fbac5 ("irqchip: Add Loongson HyperTransport Vector support") > a93f1d903fa3 ("irqchip: Add driver for Loongson-3 HyperTransport PIC controller") > b74416dba33b ("irqchip: Define EXYNOS_IRQ_COMBINER") > dbb152267908 ("irqchip: Add driver for Loongson I/O Local Interrupt Controller") > ef8c01eb64ca ("irqchip: Add Loongson PCH PIC controller") > > v4.19.143: Failed to apply! Possible dependencies: > 0145beed9d26 ("irqchip: davinci-aintc: move the driver to drivers/irqchip") > 06a287161429 ("ARM: davinci: aintc: use the new config structure") > 1fa70c7f4913 ("ARM: exynos: Enable exynos-chipid driver") > 2b6a2e74f2bf ("ARM: davinci: aintc: use a common prefix for symbols in the driver") > 2d242aa28892 ("ARM: davinci: aintc: drop GPL license boilerplate") > 4134b762eb13 ("ARM: exynos: Enable exynos-asv driver for ARCH_EXYNOS") > 74b0eac24259 ("ARM: davinci: aintc: use irq domain") > 818e915fbac5 ("irqchip: Add Loongson HyperTransport Vector support") > a93f1d903fa3 ("irqchip: Add driver for Loongson-3 HyperTransport PIC controller") > a98ca73ee348 ("ARM: davinci: wrap HW interrupt numbers with a macro") > b74416dba33b ("irqchip: Define EXYNOS_IRQ_COMBINER") > d0064594f20a ("ARM: davinci: select GENERIC_IRQ_MULTI_HANDLER") > dbb152267908 ("irqchip: Add driver for Loongson I/O Local Interrupt Controller") > de4f82a245ce ("ARM: davinci: aintc: wrap davinci_irq_init() with a helper") > ef8c01eb64ca ("irqchip: Add Loongson PCH PIC controller") > fd0f4275864d ("ARM: davinci: aintc: use the new irqchip config structure in dm* SoCs") > > v4.14.196: Failed to apply! Possible dependencies: > 0149385537e6 ("irqchip: Place CONFIG_SIFIVE_PLIC into the menu") > 1fa70c7f4913 ("ARM: exynos: Enable exynos-chipid driver") > 215f4cc0fb20 ("irqchip/meson: Add support for gpio interrupt controller") > 33c57c0d3c67 ("RISC-V: Add a basic defconfig") > 4134b762eb13 ("ARM: exynos: Enable exynos-asv driver for ARCH_EXYNOS") > 4235ff50cf98 ("irqchip/irq-goldfish-pic: Add Goldfish PIC driver") > 4a632cec8884 ("RISC-V: Enable module support in defconfig") > 67d2075ad695 ("dt-bindings: irqchip: Introduce TISCI Interrupt router bindings") > 706cffc1b912 ("irqchip/exiu: Add support for Socionext Synquacer EXIU controller") > 818e915fbac5 ("irqchip: Add Loongson HyperTransport Vector support") > 8237f8bc4f6e ("irqchip: add a SiFive PLIC driver") > 9f1463b86c13 ("irqchip/ti-sci-inta: Add support for Interrupt Aggregator driver") > a93f1d903fa3 ("irqchip: Add driver for Loongson-3 HyperTransport PIC controller") > abe45fd9f1b0 ("irqchip: Andestech Internal Vector Interrupt Controller driver") > accaf1fbfb5d ("dt-bindings: irqchip: Introduce TISCI Interrupt Aggregator bindings") > b74416dba33b ("irqchip: Define EXYNOS_IRQ_COMBINER") > c2ba80af4805 ("dt-bindings/goldfish-pic: Add device tree binding for Goldfish PIC driver") > c94fb639d546 ("irqchip: Add Kconfig menu") > ca1c4d653524 ("MAINTAINERS: Add entry for sound/soc/ti and update the OMAP audio support") > cd844b0715ce ("irqchip/ti-sci-intr: Add support for Interrupt Router driver") > dbb152267908 ("irqchip: Add driver for Loongson I/O Local Interrupt Controller") > ef8c01eb64ca ("irqchip: Add Loongson PCH PIC controller") > f55c73aef890 ("irqchip/pdc: Add PDC interrupt controller for QCOM SoCs") > > v4.9.235: Failed to apply! Possible dependencies: > 0464a53eba0a ("MIPS: Update Goldfish RTC driver maintainer email address") > 1fa70c7f4913 ("ARM: exynos: Enable exynos-chipid driver") > 215f4cc0fb20 ("irqchip/meson: Add support for gpio interrupt controller") > 33c57c0d3c67 ("RISC-V: Add a basic defconfig") > 4134b762eb13 ("ARM: exynos: Enable exynos-asv driver for ARCH_EXYNOS") > 4235ff50cf98 ("irqchip/irq-goldfish-pic: Add Goldfish PIC driver") > 4a632cec8884 ("RISC-V: Enable module support in defconfig") > 5ed34d3a4387 ("irqchip: Add UniPhier AIDET irqchip driver") > 706cffc1b912 ("irqchip/exiu: Add support for Socionext Synquacer EXIU controller") > 7a08de1d8fd2 ("dt-bindings: Add device tree binding for Goldfish RTC driver") > 818e915fbac5 ("irqchip: Add Loongson HyperTransport Vector support") > 8237f8bc4f6e ("irqchip: add a SiFive PLIC driver") > a93f1d903fa3 ("irqchip: Add driver for Loongson-3 HyperTransport PIC controller") > b74416dba33b ("irqchip: Define EXYNOS_IRQ_COMBINER") > c2ba80af4805 ("dt-bindings/goldfish-pic: Add device tree binding for Goldfish PIC driver") > c94fb639d546 ("irqchip: Add Kconfig menu") > dbb152267908 ("irqchip: Add driver for Loongson I/O Local Interrupt Controller") > ef8c01eb64ca ("irqchip: Add Loongson PCH PIC controller") > f20cc9b00c7b ("irqchip/qcom: Add IRQ combiner driver") > f22d9cdcb5eb ("rtc: goldfish: Add RTC driver for Android emulator") > f48e699ddf70 ("irqchip/aspeed-i2c-ic: Add I2C IRQ controller for Aspeed") > f55c73aef890 ("irqchip/pdc: Add PDC interrupt controller for QCOM SoCs") > > v4.4.235: Failed to apply! Possible dependencies: > 19afc3d269fe ("irqchip: i8259: Allow platforms to override poll function") > 1fa70c7f4913 ("ARM: exynos: Enable exynos-chipid driver") > 3900d6a85e66 ("ARM: EXYNOS: Split up exynos5250 SoC specific PMU data") > 4134b762eb13 ("ARM: exynos: Enable exynos-asv driver for ARCH_EXYNOS") > 73d72ed8e98c ("ARM: EXYNOS: Split up exynos4 SoC specific PMU data") > 818e915fbac5 ("irqchip: Add Loongson HyperTransport Vector support") > 8438aef01d35 ("ARM: EXYNOS: Remove redundant code from regs-pmu.h") > a93f1d903fa3 ("irqchip: Add driver for Loongson-3 HyperTransport PIC controller") > b74416dba33b ("irqchip: Define EXYNOS_IRQ_COMBINER") > bfce552d0b10 ("drivers: soc: Add support for Exynos PMU driver") > c21100c94dfa ("ARM: EXYNOS: Split up exynos3250 SoC specific PMU data") > d3bafff78331 ("ARM: EXYNOS: Enable ARCH_SUPPORTS_BIG_ENDIAN explicitly") > dbb152267908 ("irqchip: Add driver for Loongson I/O Local Interrupt Controller") > e32465429490 ("ARM: use "depends on" for SoC configs instead of "if" after prompt") > ef8c01eb64ca ("irqchip: Add Loongson PCH PIC controller") > > > NOTE: The patch will not be queued to stable trees until it is upstream. > > How should we proceed with this patch? This patch is only needed in 5.8+ Huacai > > -- > Thanks > Sasha
Hi, Marc, On Thu, Sep 10, 2020 at 6:08 PM Marc Zyngier <maz@kernel.org> wrote: > > On 2020-09-09 05:09, Huacai Chen wrote: > > Reserve legacy LPC irqs (0~15) to avoid spurious interrupts. > > How can they be spurious? Why are they enabled the first place? > > This looks like you are papering over a much bigger issue. The spurious interrupts are probably occurred after kdump and the irq number is in legacy LPC ranges. I think this is because the old kernel doesn't (and it can't) disable devices properly so there are stale interrupts in the kdump case. Huacai > > M. > > > > Cc: stable@vger.kernel.org > > Signed-off-by: Huacai Chen <chenhc@lemote.com> > > --- > > drivers/irqchip/irq-loongson-pch-pic.c | 19 ++++++++++++++++++- > > 1 file changed, 18 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/irqchip/irq-loongson-pch-pic.c > > b/drivers/irqchip/irq-loongson-pch-pic.c > > index 9bf6b9a..9f6719c 100644 > > --- a/drivers/irqchip/irq-loongson-pch-pic.c > > +++ b/drivers/irqchip/irq-loongson-pch-pic.c > > @@ -35,6 +35,7 @@ > > > > struct pch_pic { > > void __iomem *base; > > + struct irq_domain *lpc_domain; > > struct irq_domain *pic_domain; > > u32 ht_vec_base; > > raw_spinlock_t pic_lock; > > @@ -184,9 +185,9 @@ static void pch_pic_reset(struct pch_pic *priv) > > static int pch_pic_of_init(struct device_node *node, > > struct device_node *parent) > > { > > + int i, base, err; > > struct pch_pic *priv; > > struct irq_domain *parent_domain; > > - int err; > > > > priv = kzalloc(sizeof(*priv), GFP_KERNEL); > > if (!priv) > > @@ -213,6 +214,22 @@ static int pch_pic_of_init(struct device_node > > *node, > > goto iounmap_base; > > } > > > > + base = irq_alloc_descs(-1, 0, NR_IRQS_LEGACY, 0); > > + if (base < 0) { > > + pr_err("Failed to allocate LPC IRQ numbers\n"); > > + goto iounmap_base; > > + } > > + > > + priv->lpc_domain = irq_domain_add_legacy(node, NR_IRQS_LEGACY, 0, 0, > > + &irq_domain_simple_ops, NULL); > > + if (!priv->lpc_domain) { > > + pr_err("Failed to add irqdomain for LPC controller"); > > + goto iounmap_base; > > + } > > + > > + for (i = 0; i < NR_IRQS_LEGACY; i++) > > + irq_set_chip_and_handler(i, &dummy_irq_chip, handle_simple_irq); > > + > > priv->pic_domain = irq_domain_create_hierarchy(parent_domain, 0, > > PIC_COUNT, > > of_node_to_fwnode(node), > > -- > Jazz is not dead. It just smells funny...
On 2020-09-11 05:13, Huacai Chen wrote: > Hi, Marc, > > On Thu, Sep 10, 2020 at 6:08 PM Marc Zyngier <maz@kernel.org> wrote: >> >> On 2020-09-09 05:09, Huacai Chen wrote: >> > Reserve legacy LPC irqs (0~15) to avoid spurious interrupts. >> >> How can they be spurious? Why are they enabled the first place? >> >> This looks like you are papering over a much bigger issue. > The spurious interrupts are probably occurred after kdump and the irq > number is in legacy LPC ranges. I think this is because the old kernel > doesn't (and it can't) disable devices properly so there are stale > interrupts in the kdump case. I don't really understand why the old kernel can't turn the interrupts off. Most architectures are able t, why not yours? Finally, why don't you just shut these interrupts off the first place in the interrupt controller init? Adding a whole lot of kernel data structures as a band-aid doesn't strike me as the best possible idea. Not to mention that if they keep firing, all you are doing is adding extra overhead. M.
Hi, Marc, On Fri, Sep 11, 2020 at 3:50 PM Marc Zyngier <maz@kernel.org> wrote: > > On 2020-09-11 05:13, Huacai Chen wrote: > > Hi, Marc, > > > > On Thu, Sep 10, 2020 at 6:08 PM Marc Zyngier <maz@kernel.org> wrote: > >> > >> On 2020-09-09 05:09, Huacai Chen wrote: > >> > Reserve legacy LPC irqs (0~15) to avoid spurious interrupts. > >> > >> How can they be spurious? Why are they enabled the first place? > >> > >> This looks like you are papering over a much bigger issue. > > The spurious interrupts are probably occurred after kdump and the irq > > number is in legacy LPC ranges. I think this is because the old kernel > > doesn't (and it can't) disable devices properly so there are stale > > interrupts in the kdump case. > > I don't really understand why the old kernel can't turn the interrupts > off. Most architectures are able t, why not yours? > > Finally, why don't you just shut these interrupts off the first place > in the interrupt controller init? Adding a whole lot of kernel > data structures as a band-aid doesn't strike me as the best possible > idea. Not to mention that if they keep firing, all you are doing > is adding extra overhead. After tests, I found that the previous patch (patch 2 in this series) can avoid most spurious interrupts and kdump can work, so I will send V2 to drop this patch. Huacai > > M. > -- > Jazz is not dead. It just smells funny...
diff --git a/drivers/irqchip/irq-loongson-pch-pic.c b/drivers/irqchip/irq-loongson-pch-pic.c index 9bf6b9a..9f6719c 100644 --- a/drivers/irqchip/irq-loongson-pch-pic.c +++ b/drivers/irqchip/irq-loongson-pch-pic.c @@ -35,6 +35,7 @@ struct pch_pic { void __iomem *base; + struct irq_domain *lpc_domain; struct irq_domain *pic_domain; u32 ht_vec_base; raw_spinlock_t pic_lock; @@ -184,9 +185,9 @@ static void pch_pic_reset(struct pch_pic *priv) static int pch_pic_of_init(struct device_node *node, struct device_node *parent) { + int i, base, err; struct pch_pic *priv; struct irq_domain *parent_domain; - int err; priv = kzalloc(sizeof(*priv), GFP_KERNEL); if (!priv) @@ -213,6 +214,22 @@ static int pch_pic_of_init(struct device_node *node, goto iounmap_base; } + base = irq_alloc_descs(-1, 0, NR_IRQS_LEGACY, 0); + if (base < 0) { + pr_err("Failed to allocate LPC IRQ numbers\n"); + goto iounmap_base; + } + + priv->lpc_domain = irq_domain_add_legacy(node, NR_IRQS_LEGACY, 0, 0, + &irq_domain_simple_ops, NULL); + if (!priv->lpc_domain) { + pr_err("Failed to add irqdomain for LPC controller"); + goto iounmap_base; + } + + for (i = 0; i < NR_IRQS_LEGACY; i++) + irq_set_chip_and_handler(i, &dummy_irq_chip, handle_simple_irq); + priv->pic_domain = irq_domain_create_hierarchy(parent_domain, 0, PIC_COUNT, of_node_to_fwnode(node),
Reserve legacy LPC irqs (0~15) to avoid spurious interrupts. Cc: stable@vger.kernel.org Signed-off-by: Huacai Chen <chenhc@lemote.com> --- drivers/irqchip/irq-loongson-pch-pic.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-)