diff mbox series

[1/4] dt-bindings: phy: add binding for the Lantiq VRX200 and ARX300 PCIe PHYs

Message ID 20190702203523.2412-2-martin.blumenstingl@googlemail.com (mailing list archive)
State Superseded
Headers show
Series Lantiq VRX200/ARX300 PCIe PHY driver | expand

Commit Message

Martin Blumenstingl July 2, 2019, 8:35 p.m. UTC 
Add the bindings for the PCIe PHY on Lantiq VRX200 and ARX300 SoCs.
The IP block contains settings for the PHY and a PLL.
The PLL mode is configurable through a dedicated #phy-cell in .dts.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 .../bindings/phy/lantiq,vrx200-pcie-phy.yaml  | 87 +++++++++++++++++++
 .../dt-bindings/phy/phy-lantiq-vrx200-pcie.h  | 11 +++
 2 files changed, 98 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/lantiq,vrx200-pcie-phy.yaml
 create mode 100644 include/dt-bindings/phy/phy-lantiq-vrx200-pcie.h

Comments

Martin Blumenstingl July 3, 2019, 8:58 a.m. UTC | #1 
Hi Rob,

On Wed, Jul 3, 2019 at 1:34 AM Rob Herring <robh+dt@kernel.org> wrote:
>
> On Tue, Jul 2, 2019 at 2:35 PM Martin Blumenstingl
> <martin.blumenstingl@googlemail.com> wrote:
> >
> > Add the bindings for the PCIe PHY on Lantiq VRX200 and ARX300 SoCs.
> > The IP block contains settings for the PHY and a PLL.
> > The PLL mode is configurable through a dedicated #phy-cell in .dts.
> >
> > Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> > ---
> >  .../bindings/phy/lantiq,vrx200-pcie-phy.yaml  | 87 +++++++++++++++++++
> >  .../dt-bindings/phy/phy-lantiq-vrx200-pcie.h  | 11 +++
> >  2 files changed, 98 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/phy/lantiq,vrx200-pcie-phy.yaml
> >  create mode 100644 include/dt-bindings/phy/phy-lantiq-vrx200-pcie.h
> >
> > diff --git a/Documentation/devicetree/bindings/phy/lantiq,vrx200-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/lantiq,vrx200-pcie-phy.yaml
> > new file mode 100644
> > index 000000000000..b7b222e772d0
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/lantiq,vrx200-pcie-phy.yaml
> > @@ -0,0 +1,87 @@
> > +# SPDX-License-Identifier: GPL-2.0
>
> The preference is (GPL-2.0 OR BSD-2-Clause) for new bindings.
to make sure I understand this correctly:
the license is then only valid for the bindings - is it fine if the
driver uses GPL-2.0-only?

I don't have any datasheet for these SoCs so all my knowledge is based
on the GPL-2.0-only driver from the Lantiq board support package
(called "UGW").
the .yaml file is 100% my own work so I'm fine with having GPL-2.0 OR
BSD-2-Clause
however, that still has to be compatible with my driver, which I chose
to be GPL-2.0-only because that's the license from the Lantiq board
support package


Martin
Rob Herring July 3, 2019, 1:25 p.m. UTC | #2 
On Tue, Jul 2, 2019 at 5:37 PM Martin Blumenstingl
<martin.blumenstingl@googlemail.com> wrote:
>
> Hi Rob,
>
> On Wed, Jul 3, 2019 at 1:34 AM Rob Herring <robh+dt@kernel.org> wrote:
> [...]
> > > +  lantiq,rcu:
> > > +    maxItems: 1
> > > +    description: phandle to the RCU syscon
> >
> > You need to define the type (and drop maxItems):
> >
> > $ref: /schemas/types.yaml#/definitions/phandle
> thank you for this hint - the examples I used didn't have it
>
> > > +
> > > +  lantiq,rcu-endian-offset:
> > > +    $ref: /schemas/types.yaml#/definitions/uint32
> > > +    description: the offset of the endian registers for this PHY instance in the RCU syscon
> > > +
> > > +  lantiq,rcu-big-endian-mask:
> > > +    $ref: /schemas/types.yaml#/definitions/uint32
> > > +    description: the mask to set the PDI (PHY) registers for this PHY instance to big endian
> > > +
> > > +required:
> > > +  - "#phy-cells"
> > > +  - compatible
> > > +  - reg
> > > +  - clocks
> > > +  - clock-names
> > > +  - resets
> > > +  - reset-names
> > > +  - lantiq,rcu
> > > +  - lantiq,rcu-endian-offset
> > > +  - lantiq,rcu-big-endian-mask
> > > +
> > > +additionalProperties: false
> > > +
> > > +examples:
> > > +  - |
> > > +    pcie0_phy: phy@106800 {
> > > +        compatible = "lantiq,vrx200-pcie-phy";
> > > +        reg = <0x106800 0x100>;
> > > +        lantiq,rcu = <&rcu0>;
> > > +        lantiq,rcu-endian-offset = <0x4c>;
> > > +        lantiq,rcu-big-endian-mask = <0x80>; /* bit 7 */
> > > +        big-endian;
> >
> > The example will fail to validate because big-endian is not listed as
> > a property and you have 'additionalProperties: false'. So you have to
> > either list big-endian or drop additionalProperties.
> good catch, thank you.
> I'll add big-endian and little-endian as allowed (but optional) properties
>
> > Note that the examples are validated against the schema in linux-next now.
> I tested this with yesterday's linux-next tree and it didn't fail for me
> do you have any hint how I can run this validation myself?

It's not a default target:

make dt_binding_check

Rob
Rob Herring July 3, 2019, 1:30 p.m. UTC | #3 
On Wed, Jul 3, 2019 at 2:58 AM Martin Blumenstingl
<martin.blumenstingl@googlemail.com> wrote:
>
> Hi Rob,
>
> On Wed, Jul 3, 2019 at 1:34 AM Rob Herring <robh+dt@kernel.org> wrote:
> >
> > On Tue, Jul 2, 2019 at 2:35 PM Martin Blumenstingl
> > <martin.blumenstingl@googlemail.com> wrote:
> > >
> > > Add the bindings for the PCIe PHY on Lantiq VRX200 and ARX300 SoCs.
> > > The IP block contains settings for the PHY and a PLL.
> > > The PLL mode is configurable through a dedicated #phy-cell in .dts.
> > >
> > > Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> > > ---
> > >  .../bindings/phy/lantiq,vrx200-pcie-phy.yaml  | 87 +++++++++++++++++++
> > >  .../dt-bindings/phy/phy-lantiq-vrx200-pcie.h  | 11 +++
> > >  2 files changed, 98 insertions(+)
> > >  create mode 100644 Documentation/devicetree/bindings/phy/lantiq,vrx200-pcie-phy.yaml
> > >  create mode 100644 include/dt-bindings/phy/phy-lantiq-vrx200-pcie.h
> > >
> > > diff --git a/Documentation/devicetree/bindings/phy/lantiq,vrx200-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/lantiq,vrx200-pcie-phy.yaml
> > > new file mode 100644
> > > index 000000000000..b7b222e772d0
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/phy/lantiq,vrx200-pcie-phy.yaml
> > > @@ -0,0 +1,87 @@
> > > +# SPDX-License-Identifier: GPL-2.0
> >
> > The preference is (GPL-2.0 OR BSD-2-Clause) for new bindings.
> to make sure I understand this correctly:
> the license is then only valid for the bindings - is it fine if the
> driver uses GPL-2.0-only?

Yes, as this isn't derived from the driver code nor used by the driver
code (though that would be fine).

BTW, 'GPL-2.0-only' is the newer, preferred form of 'GPL-2.0', so I
guess we should be using (GPL-2.0-only OR BSD-2-Clause).

> I don't have any datasheet for these SoCs so all my knowledge is based
> on the GPL-2.0-only driver from the Lantiq board support package
> (called "UGW").
> the .yaml file is 100% my own work so I'm fine with having GPL-2.0 OR
> BSD-2-Clause
> however, that still has to be compatible with my driver, which I chose
> to be GPL-2.0-only because that's the license from the Lantiq board
> support package
>
>
> Martin
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/phy/lantiq,vrx200-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/lantiq,vrx200-pcie-phy.yaml
new file mode 100644
index 000000000000..b7b222e772d0
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/lantiq,vrx200-pcie-phy.yaml
@@ -0,0 +1,87 @@ 
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/lantiq,vrx200-pcie-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Lantiq VRX200 and ARX300 PCIe PHY Device Tree Bindings
+
+maintainers:
+  - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+
+properties:
+  "#phy-cells":
+    const: 1
+    description: selects the PHY mode as defined in <dt-bindings/phy/phy-lantiq-vrx200-pcie.h>
+
+  compatible:
+    enum:
+      - lantiq,vrx200-pcie-phy
+      - lantiq,arx300-pcie-phy
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: PHY module clock
+      - description: PDI register clock
+
+  clock-names:
+    items:
+      - const: phy
+      - const: pdi
+
+  resets:
+    items:
+      - description: exclusive PHY reset line
+      - description: shared reset line between the PCIe PHY and PCIe controller
+
+  resets-names:
+    items:
+      - const: phy
+      - const: pcie
+
+  lantiq,rcu:
+    maxItems: 1
+    description: phandle to the RCU syscon
+
+  lantiq,rcu-endian-offset:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: the offset of the endian registers for this PHY instance in the RCU syscon
+
+  lantiq,rcu-big-endian-mask:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: the mask to set the PDI (PHY) registers for this PHY instance to big endian
+
+required:
+  - "#phy-cells"
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - resets
+  - reset-names
+  - lantiq,rcu
+  - lantiq,rcu-endian-offset
+  - lantiq,rcu-big-endian-mask
+
+additionalProperties: false
+
+examples:
+  - |
+    pcie0_phy: phy@106800 {
+        compatible = "lantiq,vrx200-pcie-phy";
+        reg = <0x106800 0x100>;
+        lantiq,rcu = <&rcu0>;
+        lantiq,rcu-endian-offset = <0x4c>;
+        lantiq,rcu-big-endian-mask = <0x80>; /* bit 7 */
+        big-endian;
+        clocks = <&pmu PCIE_PHY>, <&pmu PCIE_PHY_PDI>;
+        clock-names = "phy", "pdi";
+        resets = <&reset0 12 24>, <&reset0 22 22>;
+        reset-names = "phy", "pcie";
+        #phy-cells = <1>;
+    };
+
+...
diff --git a/include/dt-bindings/phy/phy-lantiq-vrx200-pcie.h b/include/dt-bindings/phy/phy-lantiq-vrx200-pcie.h
new file mode 100644
index 000000000000..95a7896356d6
--- /dev/null
+++ b/include/dt-bindings/phy/phy-lantiq-vrx200-pcie.h
@@ -0,0 +1,11 @@ 
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2019 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+ */
+
+#define LANTIQ_PCIE_PHY_MODE_25MHZ		0
+#define LANTIQ_PCIE_PHY_MODE_25MHZ_SSC		1
+#define LANTIQ_PCIE_PHY_MODE_36MHZ		2
+#define LANTIQ_PCIE_PHY_MODE_36MHZ_SSC		3
+#define LANTIQ_PCIE_PHY_MODE_100MHZ		4
+#define LANTIQ_PCIE_PHY_MODE_100MHZ_SSC		5