From patchwork Wed Jul 24 02:23:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chuanhong Guo X-Patchwork-Id: 11055607 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3D25D912 for ; Wed, 24 Jul 2019 02:24:36 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2DA0B2875F for ; Wed, 24 Jul 2019 02:24:36 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1E6CC28780; Wed, 24 Jul 2019 02:24:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9AD2D286E4 for ; Wed, 24 Jul 2019 02:24:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728914AbfGXCYa (ORCPT ); Tue, 23 Jul 2019 22:24:30 -0400 Received: from mail-pl1-f194.google.com ([209.85.214.194]:41690 "EHLO mail-pl1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728052AbfGXCY3 (ORCPT ); Tue, 23 Jul 2019 22:24:29 -0400 Received: by mail-pl1-f194.google.com with SMTP id m9so21258635pls.8; Tue, 23 Jul 2019 19:24:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fAOxzZw/MQyA9eCxg3dz/9JXY348XgvfL/0jCf3qhSo=; b=qmDQaCCkzJM3tjqNb60YdqegPoAIVlt2jrTXEsB4JIVL9+TSifudJXqGNz4bPLWjys 4ziN8qz2uyYVOL4dIzBZ9gAygM4u2hTVCBBLIZxv5FcVBAvJVJ4ubhBNK2XB0Z18eJdB voyzv+FAto/5JnhDCOH8qG0vh8Wh6yOjMFaEQvH3bEvln6XMM5kRU+lCW9WrKelrmmrv ODvpbLIN87xCM4yLxOMJDOnUQLbTlOc3bL9b4VmgqRWLn7+4tqZFyC/sKyQzg+qoW1e3 btt6KbHTn2DPVIrrjRK9nUJ7Bci1W9L2N841mtxGkN1p0bw+4/NWvS1Opt4lDz+ITHwT wOGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fAOxzZw/MQyA9eCxg3dz/9JXY348XgvfL/0jCf3qhSo=; b=jiNrzu6UeoYJcdt+vcIN7tV5YGbpaGenqnXgYzVpIv2p9AJnc3a9y8nboEiyhnaXkH TdeB9DzdhLRH7Y/pKwr+ToeU7KKqXudHqE9KN4wZddvOEIVMb0LEMQVBMJA0LPyqmUCI arnY5rUGjxZiw+d1IxSIy8QKMTjIKfTm14Kz6CR0y03IfMKcZrRF33kLC94oQaT2kw4y 8oBA2dlcqICmBcRwQAzAeljQak9ynMG5w44teTehLp3AidlEFnEzHVcpgojDgtmqxX2o xtVXUi7zbe7jogiNPvRRYoTnBenewV6O39BHeUNJIKj2Z6DVb5skTsweSk9exJMKOl9u E2vg== X-Gm-Message-State: APjAAAVEfqEMhK5dEWULWTm8TClYTN0FVXugIpgMhm/4d7NL/yCkw6Lu vyyd2fRxumNA1iZU/rZbdeSKec9HM3o= X-Google-Smtp-Source: APXvYqzLIb9de4c0yjoqKVOV+8sdtTEYw/IMzFC9CzQRUgMtpRa75hCHQ45w4ZMwm0g5wFk7nD4VgA== X-Received: by 2002:a17:902:f095:: with SMTP id go21mr85051752plb.58.1563935068782; Tue, 23 Jul 2019 19:24:28 -0700 (PDT) Received: from guoguo-omen-lan.lan ([107.151.139.128]) by smtp.gmail.com with ESMTPSA id s185sm63468029pgs.67.2019.07.23.19.24.23 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Tue, 23 Jul 2019 19:24:28 -0700 (PDT) From: Chuanhong Guo To: linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list), linux-mips@vger.kernel.org (open list:MIPS), devel@driverdev.osuosl.org (open list:STAGING SUBSYSTEM) Cc: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Ralf Baechle , Paul Burton , James Hogan , John Crispin , Greg Kroah-Hartman , Weijie Gao , NeilBrown , Chuanhong Guo Subject: [PATCH v2 3/6] MIPS: ralink: add clock device providing cpu/bus clock for mt7621 Date: Wed, 24 Jul 2019 10:23:07 +0800 Message-Id: <20190724022310.28010-4-gch981213@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190724022310.28010-1-gch981213@gmail.com> References: <20190724022310.28010-1-gch981213@gmail.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP For a long time the mt7621 uses a fixed cpu clock which causes a problem if the cpu frequency is not 880MHz. This patch adds cpu/bus clock calculation code and binds clocks to mt7621-pll node. Ported from OpenWrt: c7ca224299 ramips: fix cpu clock of mt7621 and add dt clk devices Signed-off-by: Weijie Gao Signed-off-by: Chuanhong Guo --- Changes since v1: 1. split patch. 2. calculate clocks using the function called by CLK_OF_DECLARE drop direct function call in timer-gic.c of ralink_clk_init 3. drop assignment of mips-hpt-frequency arch/mips/include/asm/mach-ralink/mt7621.h | 20 ++++++ arch/mips/ralink/mt7621.c | 77 ++++++++++++++++++++++ 2 files changed, 97 insertions(+) diff --git a/arch/mips/include/asm/mach-ralink/mt7621.h b/arch/mips/include/asm/mach-ralink/mt7621.h index 65483a4681ab..51a6e51aef3f 100644 --- a/arch/mips/include/asm/mach-ralink/mt7621.h +++ b/arch/mips/include/asm/mach-ralink/mt7621.h @@ -17,6 +17,10 @@ #define SYSC_REG_CHIP_REV 0x0c #define SYSC_REG_SYSTEM_CONFIG0 0x10 #define SYSC_REG_SYSTEM_CONFIG1 0x14 +#define SYSC_REG_CLKCFG0 0x2c +#define SYSC_REG_CUR_CLK_STS 0x44 + +#define MEMC_REG_CPU_PLL 0x648 #define CHIP_REV_PKG_MASK 0x1 #define CHIP_REV_PKG_SHIFT 16 @@ -24,6 +28,22 @@ #define CHIP_REV_VER_SHIFT 8 #define CHIP_REV_ECO_MASK 0xf +#define XTAL_MODE_SEL_MASK 0x7 +#define XTAL_MODE_SEL_SHIFT 6 + +#define CPU_CLK_SEL_MASK 0x3 +#define CPU_CLK_SEL_SHIFT 30 + +#define CUR_CPU_FDIV_MASK 0x1f +#define CUR_CPU_FDIV_SHIFT 8 +#define CUR_CPU_FFRAC_MASK 0x1f +#define CUR_CPU_FFRAC_SHIFT 0 + +#define CPU_PLL_PREDIV_MASK 0x3 +#define CPU_PLL_PREDIV_SHIFT 12 +#define CPU_PLL_FBDIV_MASK 0x7f +#define CPU_PLL_FBDIV_SHIFT 4 + #define MT7621_DRAM_BASE 0x0 #define MT7621_DDR2_SIZE_MIN 32 #define MT7621_DDR2_SIZE_MAX 256 diff --git a/arch/mips/ralink/mt7621.c b/arch/mips/ralink/mt7621.c index ba39f3f3a7c7..baf9033a67b4 100644 --- a/arch/mips/ralink/mt7621.c +++ b/arch/mips/ralink/mt7621.c @@ -7,12 +7,16 @@ #include #include +#include +#include +#include #include #include #include #include #include +#include #include @@ -103,11 +107,84 @@ static struct rt2880_pmx_group mt7621_pinmux_data[] = { { 0 } }; +static struct clk *clks[MT7621_CLK_MAX]; +static struct clk_onecell_data clk_data = { + .clks = clks, + .clk_num = ARRAY_SIZE(clks), +}; + phys_addr_t mips_cpc_default_phys_base(void) { panic("Cannot detect cpc address"); } +static struct clk *__init mt7621_add_sys_clkdev( + const char *id, unsigned long rate) +{ + struct clk *clk; + int err; + + clk = clk_register_fixed_rate(NULL, id, NULL, 0, rate); + if (IS_ERR(clk)) + panic("failed to allocate %s clock structure", id); + + err = clk_register_clkdev(clk, id, NULL); + if (err) + panic("unable to register %s clock device", id); + + return clk; +} + +static void __init mt7621_clocks_init(struct device_node *np) +{ + const static u32 prediv_tbl[] = {0, 1, 2, 2}; + u32 syscfg, xtal_sel, clkcfg, clk_sel, curclk, ffiv, ffrac; + u32 pll, prediv, fbdiv; + u32 xtal_clk, cpu_clk, bus_clk; + + syscfg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0); + xtal_sel = (syscfg >> XTAL_MODE_SEL_SHIFT) & XTAL_MODE_SEL_MASK; + + clkcfg = rt_sysc_r32(SYSC_REG_CLKCFG0); + clk_sel = (clkcfg >> CPU_CLK_SEL_SHIFT) & CPU_CLK_SEL_MASK; + + curclk = rt_sysc_r32(SYSC_REG_CUR_CLK_STS); + ffiv = (curclk >> CUR_CPU_FDIV_SHIFT) & CUR_CPU_FDIV_MASK; + ffrac = (curclk >> CUR_CPU_FFRAC_SHIFT) & CUR_CPU_FFRAC_MASK; + + if (xtal_sel <= 2) + xtal_clk = 20 * 1000 * 1000; + else if (xtal_sel <= 5) + xtal_clk = 40 * 1000 * 1000; + else + xtal_clk = 25 * 1000 * 1000; + + switch (clk_sel) { + case 0: + cpu_clk = 500 * 1000 * 1000; + break; + case 1: + pll = rt_memc_r32(MEMC_REG_CPU_PLL); + fbdiv = (pll >> CPU_PLL_FBDIV_SHIFT) & CPU_PLL_FBDIV_MASK; + prediv = (pll >> CPU_PLL_PREDIV_SHIFT) & CPU_PLL_PREDIV_MASK; + cpu_clk = ((fbdiv + 1) * xtal_clk) >> prediv_tbl[prediv]; + break; + default: + cpu_clk = xtal_clk; + } + + cpu_clk = cpu_clk / ffiv * ffrac; + bus_clk = cpu_clk / 4; + + clks[MT7621_CLK_CPU] = mt7621_add_sys_clkdev("cpu", cpu_clk); + clks[MT7621_CLK_BUS] = mt7621_add_sys_clkdev("bus", bus_clk); + + pr_info("CPU Clock: %dMHz\n", cpu_clk / 1000000); + + of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); +} +CLK_OF_DECLARE(mt7621_clk, "mediatek,mt7621-pll", mt7621_clocks_init); + void __init ralink_of_remap(void) { rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc");