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received-spf: None (protection.outlook.com: wavecomp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: tm543mOujwZOy5RZLSJZ7ZVFt8AL/BITyg43+5TszTsUWL76vCZepL4tuwuoAKo71DX+wEX3OVVpasPB1PLObioqd5TL9srlbi+ux6NuyviGjsPUoWe3IGYMIJ77Ecs7W2FoFB/3KvC7V509AIOZTeVuIORpW38lrq8bSpXclIOu17KpczWWHGrwXruvJBgmqpyxe1cHzYDoQ7ZaMaAox/hBlGjtyIa9qX8hpnZl7nZ8DKR5e1FkhgAF/+EcaNgxwNgS1fkHTMryU7sQbah6+QArp8CBRStfiEwLN74pkkqUH1tfYl5GZVQGcONoru+lzajRRTVdbNYeXX+Q/uuFTn326D6y35Otdsi9ujviV6LNHLTa8RYXsQs7ZnPYIxuKCfuNVG1y0SGuwn9YDdKp/jYpI1ugk6w6PZCqUOFmdMk= MIME-Version: 1.0 X-OriginatorOrg: mips.com X-MS-Exchange-CrossTenant-Network-Message-Id: be9a93b3-c89e-4236-71cc-08d745fb21b6 X-MS-Exchange-CrossTenant-originalarrivaltime: 30 Sep 2019 23:08:40.2916 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 463607d3-1db3-40a0-8a29-970c56230104 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: dInZDDzcOQB6jQRqIfF0QtO2RIHfa98dzJwJsDKRTx6+hyHodX+04+uZlTzM2F5s9fg9DoMMqlQ0igGGFaFKQQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR2201MB1022 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org When building a kernel configured to support Loongson3 LL/SC workarounds (ie. CONFIG_CPU_LOONGSON3_WORKAROUNDS=y) the inline assembly in __xchg_asm() & __cmpxchg_asm() already emits completion barriers, and as such we don't need to emit extra barriers from the xchg() or cmpxchg() macros. Add compile-time constant checks causing us to omit the redundant memory barriers. Signed-off-by: Paul Burton --- arch/mips/include/asm/cmpxchg.h | 26 +++++++++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) diff --git a/arch/mips/include/asm/cmpxchg.h b/arch/mips/include/asm/cmpxchg.h index fc121d20a980..820df68e32e1 100644 --- a/arch/mips/include/asm/cmpxchg.h +++ b/arch/mips/include/asm/cmpxchg.h @@ -94,7 +94,13 @@ static inline unsigned long __xchg(volatile void *ptr, unsigned long x, ({ \ __typeof__(*(ptr)) __res; \ \ - smp_mb__before_llsc(); \ + /* \ + * In the Loongson3 workaround case __xchg_asm() already \ + * contains a completion barrier prior to the LL, so we don't \ + * need to emit an extra one here. \ + */ \ + if (!__SYNC_loongson3_war) \ + smp_mb__before_llsc(); \ \ __res = (__typeof__(*(ptr))) \ __xchg((ptr), (unsigned long)(x), sizeof(*(ptr))); \ @@ -179,9 +185,23 @@ static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old, ({ \ __typeof__(*(ptr)) __res; \ \ - smp_mb__before_llsc(); \ + /* \ + * In the Loongson3 workaround case __cmpxchg_asm() already \ + * contains a completion barrier prior to the LL, so we don't \ + * need to emit an extra one here. \ + */ \ + if (!__SYNC_loongson3_war) \ + smp_mb__before_llsc(); \ + \ __res = cmpxchg_local((ptr), (old), (new)); \ - smp_llsc_mb(); \ + \ + /* \ + * In the Loongson3 workaround case __cmpxchg_asm() already \ + * contains a completion barrier after the SC, so we don't \ + * need to emit an extra one here. \ + */ \ + if (!__SYNC_loongson3_war) \ + smp_llsc_mb(); \ \ __res; \ })