From patchwork Fri Feb 21 05:09:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 11395565 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 08299138D for ; Fri, 21 Feb 2020 05:15:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id DC250222C4 for ; Fri, 21 Feb 2020 05:15:27 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=flygoat.com header.i=jiaxun.yang@flygoat.com header.b="FXZ5VPrp" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726410AbgBUFP1 (ORCPT ); Fri, 21 Feb 2020 00:15:27 -0500 Received: from sender3-op-o12.zoho.com.cn ([124.251.121.243]:17858 "EHLO sender3-op-o12.zoho.com.cn" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726018AbgBUFP1 (ORCPT ); Fri, 21 Feb 2020 00:15:27 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1582262057; s=mail; d=flygoat.com; i=jiaxun.yang@flygoat.com; h=From:To:Cc:Message-ID:Subject:Date:In-Reply-To:References:MIME-Version:Content-Transfer-Encoding:Content-Type; bh=utHjWgS/9MgbWFbTCvxGYRCRLUfEMYG7F22NuP75MMk=; b=FXZ5VPrpIDkc90msEBKP9ng5ic5PuYRKNeBvW7emxr9G3irqpYysIDFYPWFCrAU9 rsOVgSQUHPoS+YtKiXLbFbw9TBiVb+6wcBUkglvT3plFk1lJ1hZ04DMgYGT46OeIRoY NK5evtCxdVS0CrFHfHm9hD+iOX8t5F0N4UjuP9oc= Received: from localhost.localdomain (39.155.141.144 [39.155.141.144]) by mx.zoho.com.cn with SMTPS id 1582262055106303.98857959372856; Fri, 21 Feb 2020 13:14:15 +0800 (CST) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: Jiaxun Yang , Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , Mark Rutland , Ralf Baechle , Paul Burton , Huacai Chen , Allison Randal , Greg Kroah-Hartman , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Message-ID: <20200221050942.507775-11-jiaxun.yang@flygoat.com> Subject: [PATCH v4 10/10] MIPS: Loongson64: Move MIPS_CPU_IRQ_BASE Date: Fri, 21 Feb 2020 13:09:25 +0800 X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200221050942.507775-1-jiaxun.yang@flygoat.com> References: <20200221050942.507775-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 X-ZohoCNMailClient: External Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org To prevent CPU IRQ collide with PCH IRQ, we move down CPU IRQ BASE to 16. Signed-off-by: Jiaxun Yang --- arch/mips/include/asm/mach-loongson64/irq.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/include/asm/mach-loongson64/irq.h b/arch/mips/include/asm/mach-loongson64/irq.h index 12208119aac0..1ce2e0bbe305 100644 --- a/arch/mips/include/asm/mach-loongson64/irq.h +++ b/arch/mips/include/asm/mach-loongson64/irq.h @@ -5,7 +5,7 @@ #include /* cpu core interrupt numbers */ -#define MIPS_CPU_IRQ_BASE 56 +#define MIPS_CPU_IRQ_BASE 16 #include_next #endif /* __ASM_MACH_LOONGSON64_IRQ_H_ */