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[23/31] sh: implement flush_icache_user_range

Message ID	20200510075510.987823-24-hch@lst.de (mailing list archive)
State	Superseded
Headers	show Return-Path: <SRS0=g+8T=6Y=vger.kernel.org=linux-mips-owner@kernel.org> From: Christoph Hellwig <hch@lst.de> To: Andrew Morton <akpm@linux-foundation.org>, Arnd Bergmann <arnd@arndb.de>, Roman Zippel <zippel@linux-m68k.org> Cc: Jessica Yu <jeyu@kernel.org>, Michal Simek <monstr@monstr.eu>, x86@kernel.org, linux-alpha@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-c6x-dev@linux-c6x.org, linux-hexagon@vger.kernel.org, linux-ia64@vger.kernel.org, linux-m68k@lists.linux-m68k.org, linux-mips@vger.kernel.org, openrisc@lists.librecores.org, linuxppc-dev@lists.ozlabs.org, linux-riscv@lists.infradead.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-arch@vger.kernel.org, linux-mm@kvack.org, linux-um@lists.infradead.org, linux-xtensa@linux-xtensa.org, linux-fsdevel@vger.kernel.org Subject: [PATCH 23/31] sh: implement flush_icache_user_range Date: Sun, 10 May 2020 09:55:02 +0200 Message-Id: <20200510075510.987823-24-hch@lst.de> In-Reply-To: <20200510075510.987823-1-hch@lst.de> References: <20200510075510.987823-1-hch@lst.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-mips-owner@vger.kernel.org Precedence: bulk
Series	[01/31] arm: fix the flush_icache_range arguments in set_fiq_handler \| expand [01/31] arm: fix the flush_icache_range arguments in set_fiq_handler [02/31] arm64: fix the flush_icache_range arguments in machine_kexec [03/31] MIPS: unexport __flush_icache_user_range [04/31] nds32: unexport flush_icache_page [05/31] powerpc: unexport flush_icache_user_range [06/31] unicore32: remove flush_cache_user_range [07/31] asm-generic: fix the inclusion guards for cacheflush.h [08/31] asm-generic: don't include <linux/mm.h> in cacheflush.h [09/31] asm-generic: improve the flush_dcache_page stub [10/31] alpha: use asm-generic/cacheflush.h [11/31] arm64: use asm-generic/cacheflush.h [12/31] c6x: use asm-generic/cacheflush.h [13/31] hexagon: use asm-generic/cacheflush.h [14/31] ia64: use asm-generic/cacheflush.h [15/31] microblaze: use asm-generic/cacheflush.h [16/31] m68knommu: use asm-generic/cacheflush.h [17/31] openrisc: use asm-generic/cacheflush.h [18/31] powerpc: use asm-generic/cacheflush.h [19/31] riscv: use asm-generic/cacheflush.h [20/31] arm,sparc,unicore32: remove flush_icache_user_range [21/31] mm: rename flush_icache_user_range to flush_icache_user_page [22/31] asm-generic: add a flush_icache_user_range stub [23/31] sh: implement flush_icache_user_range [24/31] xtensa: implement flush_icache_user_range [25/31] arm: rename flush_cache_user_range to flush_icache_user_range [26/31] m68k: implement flush_icache_user_range [27/31] exec: only build read_code when needed [28/31] exec: use flush_icache_user_range in read_code [29/31] binfmt_flat: use flush_icache_user_range [30/31] nommu: use flush_icache_user_range in brk and mmap [31/31] module: move the set_fs hack for flush_icache_range to m68k

Commit Message

Christoph Hellwig May 10, 2020, 7:55 a.m. UTC

The SuperH implementation of flush_icache_range seems to be able to
cope with user addresses.  Just define flush_icache_user_range to
flush_icache_range.

Signed-off-by: Christoph Hellwig <hch@lst.de>
---
 arch/sh/include/asm/cacheflush.h | 1 +
 1 file changed, 1 insertion(+)

diff mbox series

Patch

diff --git a/arch/sh/include/asm/cacheflush.h b/arch/sh/include/asm/cacheflush.h
index b932e42ef0284..fe7400079b97b 100644
--- a/arch/sh/include/asm/cacheflush.h
+++ b/arch/sh/include/asm/cacheflush.h
@@ -46,6 +46,7 @@  extern void flush_cache_range(struct vm_area_struct *vma,
 #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
 extern void flush_dcache_page(struct page *page);
 extern void flush_icache_range(unsigned long start, unsigned long end);
+#define flush_icache_user_range flush_icache_range
 extern void flush_icache_page(struct vm_area_struct *vma,
 				 struct page *page);
 extern void flush_cache_sigtramp(unsigned long address);