From patchwork Fri May 15 10:47:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 11551145 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 40733739 for ; Fri, 15 May 2020 10:49:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3326120758 for ; Fri, 15 May 2020 10:49:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728376AbgEOKtG (ORCPT ); Fri, 15 May 2020 06:49:06 -0400 Received: from mail.baikalelectronics.com ([87.245.175.226]:35448 "EHLO mail.baikalelectronics.ru" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728129AbgEOKtD (ORCPT ); Fri, 15 May 2020 06:49:03 -0400 Received: from localhost (unknown [127.0.0.1]) by mail.baikalelectronics.ru (Postfix) with ESMTP id B0F748000658; Fri, 15 May 2020 10:49:00 +0000 (UTC) X-Virus-Scanned: amavisd-new at baikalelectronics.ru Received: from mail.baikalelectronics.ru ([127.0.0.1]) by localhost (mail.baikalelectronics.ru [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Q12HfA6xiRhZ; Fri, 15 May 2020 13:48:55 +0300 (MSK) From: Serge Semin To: Mark Brown CC: Serge Semin , Serge Semin , Georgy Vlasov , Ramil Zaripov , Alexey Malahov , Thomas Bogendoerfer , Paul Burton , Ralf Baechle , Arnd Bergmann , Allison Randal , Andy Shevchenko , Gareth Williams , Rob Herring , , , Thomas Gleixner , Wan Ahmad Zainie , Jarkko Nikula , , Subject: [PATCH v2 09/19] spi: dw: Parameterize the DMA Rx/Tx burst length Date: Fri, 15 May 2020 13:47:48 +0300 Message-ID: <20200515104758.6934-10-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20200515104758.6934-1-Sergey.Semin@baikalelectronics.ru> References: <20200508132943.9826-1-Sergey.Semin@baikalelectronics.ru> <20200515104758.6934-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org It isn't good to have numeric literals in the code especially if there are multiple of them and they are related. Moreover in current implementation the Tx DMA transfer activation level isn't optimal, since it's hardwired to be at 16-32 bytes level, while it's better to keep the SPI FIFO buffer as full as possible until all available data is submitted. So lets introduce the DMA burst level parametrization macros with optimal values - issue Rx transfer if at least 16 bytes are available in the buffer and execute Tx transaction if at least 16 bytes room is opened in SPI Tx FIFO. Co-developed-by: Georgy Vlasov Signed-off-by: Georgy Vlasov Co-developed-by: Ramil Zaripov Signed-off-by: Ramil Zaripov Signed-off-by: Serge Semin Cc: Alexey Malahov Cc: Thomas Bogendoerfer Cc: Paul Burton Cc: Ralf Baechle Cc: Arnd Bergmann Cc: Allison Randal Cc: Andy Shevchenko Cc: Gareth Williams Cc: Rob Herring Cc: linux-mips@vger.kernel.org Cc: devicetree@vger.kernel.org --- drivers/spi/spi-dw-mid.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-dw-mid.c b/drivers/spi/spi-dw-mid.c index ca8813a693d8..e43914dbcadf 100644 --- a/drivers/spi/spi-dw-mid.c +++ b/drivers/spi/spi-dw-mid.c @@ -20,7 +20,9 @@ #define WAIT_RETRIES 5 #define RX_BUSY 0 +#define RX_BURST_LEVEL 16 #define TX_BUSY 1 +#define TX_BURST_LEVEL 16 static bool mid_spi_dma_chan_filter(struct dma_chan *chan, void *param) { @@ -193,7 +195,7 @@ static struct dma_async_tx_descriptor *dw_spi_dma_prepare_tx(struct dw_spi *dws, memset(&txconf, 0, sizeof(txconf)); txconf.direction = DMA_MEM_TO_DEV; txconf.dst_addr = dws->dma_addr; - txconf.dst_maxburst = 16; + txconf.dst_maxburst = TX_BURST_LEVEL; txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; txconf.dst_addr_width = convert_dma_width(dws->n_bytes); txconf.device_fc = false; @@ -266,7 +268,7 @@ static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws, memset(&rxconf, 0, sizeof(rxconf)); rxconf.direction = DMA_DEV_TO_MEM; rxconf.src_addr = dws->dma_addr; - rxconf.src_maxburst = 16; + rxconf.src_maxburst = RX_BURST_LEVEL; rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; rxconf.src_addr_width = convert_dma_width(dws->n_bytes); rxconf.device_fc = false; @@ -291,8 +293,8 @@ static int mid_spi_dma_setup(struct dw_spi *dws, struct spi_transfer *xfer) { u16 imr = 0, dma_ctrl = 0; - dw_writel(dws, DW_SPI_DMARDLR, 0xf); - dw_writel(dws, DW_SPI_DMATDLR, 0x10); + dw_writel(dws, DW_SPI_DMARDLR, RX_BURST_LEVEL - 1); + dw_writel(dws, DW_SPI_DMATDLR, dws->fifo_len - TX_BURST_LEVEL); if (xfer->tx_buf) { dma_ctrl |= SPI_DMA_TDMAE;