| Message ID | 20200521003443.11385-9-Sergey.Semin@baikalelectronics.ru (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | mips: Prepare MIPS-arch code for Baikal-T1 SoC support | expand |
On Thu, May 21, 2020 at 03:34:37AM +0300, Serge Semin wrote: > Indeed according to the MIPS32 Privileged Resource Architecgture the MAAR > pair register address field either takes [12:31] bits for non-XPA systems > and [12:55] otherwise. In any case the current address mask is just > wrong for 64-bit and 32-bits XPA chips. So lets extend it to 59-bits > of physical address value. This shall cover the 64-bits architecture and > systems with XPA enabled, and won't cause any problem for non-XPA 32-bit > systems, since address values exceeding the architecture specific MAAR > mask will be just truncated with setting zeros in the unsupported upper > bits. > > Co-developed-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru> > Signed-off-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru> > Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> > Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> > Cc: Paul Burton <paulburton@kernel.org> > Cc: Ralf Baechle <ralf@linux-mips.org> > Cc: Arnd Bergmann <arnd@arndb.de> > Cc: Rob Herring <robh+dt@kernel.org> > Cc: devicetree@vger.kernel.org > > --- > > Changelog v3: > - In accordance with MIPS32/64 Privileged Resource Architecture Extend > the MAAR Addr mask to value [12:55] instead of P5600-specific [12:35]. > --- > arch/mips/include/asm/mipsregs.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) applied to mips-next. Thomas.
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 039ebd913f00..30d9e28d01b0 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -775,7 +775,7 @@ /* MAAR bit definitions */ #define MIPS_MAAR_VH (_U64CAST_(1) << 63) -#define MIPS_MAAR_ADDR ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12) +#define MIPS_MAAR_ADDR GENMASK_ULL(55, 12) #define MIPS_MAAR_ADDR_SHIFT 12 #define MIPS_MAAR_S (_ULCAST_(1) << 1) #define MIPS_MAAR_VL (_ULCAST_(1) << 0)