diff mbox series

MIPS: SNI: Fix MIPS_L1_CACHE_SHIFT

Message ID 20200914160500.21356-1-tsbogend@alpha.franken.de (mailing list archive)
State Accepted
Commit 564c836fd945a94b5dd46597d6b7adb464092650
Headers show
Series MIPS: SNI: Fix MIPS_L1_CACHE_SHIFT | expand

Commit Message

Thomas Bogendoerfer Sept. 14, 2020, 4:05 p.m. UTC 
Commit 930beb5ac09a ("MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>") forgot
to select the correct MIPS_L1_CACHE_SHIFT for SNI RM. This breaks non
coherent DMA because of a wrong allocation alignment.

Fixes: 930beb5ac09a ("MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>")
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
---
 arch/mips/Kconfig | 1 +
 1 file changed, 1 insertion(+)

Comments

Thomas Bogendoerfer Sept. 17, 2020, 9:41 a.m. UTC | #1 
On Mon, Sep 14, 2020 at 06:05:00PM +0200, Thomas Bogendoerfer wrote:
> Commit 930beb5ac09a ("MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>") forgot
> to select the correct MIPS_L1_CACHE_SHIFT for SNI RM. This breaks non
> coherent DMA because of a wrong allocation alignment.
> 
> Fixes: 930beb5ac09a ("MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>")
> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> ---
>  arch/mips/Kconfig | 1 +
>  1 file changed, 1 insertion(+)

applied to mips-fixes.

Thomas.
diff mbox series

Patch

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index c95fa3a2484c..8f328298f8cc 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -877,6 +877,7 @@  config SNI_RM
 	select I8253
 	select I8259
 	select ISA
+	select MIPS_L1_CACHE_SHIFT_6
 	select SWAP_IO_SPACE if CPU_BIG_ENDIAN
 	select SYS_HAS_CPU_R4X00
 	select SYS_HAS_CPU_R5000