| Message ID | 20201007101704.110101-1-tsbogend@alpha.franken.de (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 46dd40aa376c8158b6aa17510079caf5c3af6237 |
| Headers | show |
| Series | MIPS: SGI-IP28: disable use of ll/sc in kernel | expand |
On Wed, Oct 07, 2020 at 12:17:04PM +0200, Thomas Bogendoerfer wrote: > SGI-IP28 systems only use broken R10k rev 2.5 CPUs, which could lock > up, if ll/sc sequences are issued in certain order. Since those systems > are all non-SMP, we can disable ll/sc usage in kernel. > > Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> > --- > arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) applied to mips-next. Thomas.
diff --git a/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h index ba8b4e30b3e2..613bbc10c1f2 100644 --- a/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h @@ -25,7 +25,7 @@ #define cpu_has_mcheck 0 #define cpu_has_ejtag 0 -#define cpu_has_llsc 1 +#define cpu_has_llsc 0 #define cpu_has_vtag_icache 0 #define cpu_has_dc_aliases 0 /* see probe_pcache() */ #define cpu_has_ic_fills_f_dc 0
SGI-IP28 systems only use broken R10k rev 2.5 CPUs, which could lock up, if ll/sc sequences are issued in certain order. Since those systems are all non-SMP, we can disable ll/sc usage in kernel. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> --- arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)