| Message ID | 20201111163013.29412-3-sergio.paracuellos@gmail.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | MIPS: ralink: add CPU clock detection and clock gate driver for MT7621 | expand |
On Wed, 11 Nov 2020 17:30:08 +0100, Sergio Paracuellos wrote: > Adds device tree binding documentation for PLL controller in > the MT7621 SOC. > > Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> > --- > .../bindings/clock/mediatek,mt7621-pll.yaml | 51 +++++++++++++++++++ > 1 file changed, 51 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.yaml > Reviewed-by: Rob Herring <robh@kernel.org>
Hi Rob, On Mon, Nov 16, 2020 at 8:16 PM Rob Herring <robh@kernel.org> wrote: > > On Wed, 11 Nov 2020 17:30:08 +0100, Sergio Paracuellos wrote: > > Adds device tree binding documentation for PLL controller in > > the MT7621 SOC. > > > > Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> > > --- > > .../bindings/clock/mediatek,mt7621-pll.yaml | 51 +++++++++++++++++++ > > 1 file changed, 51 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.yaml > > > > Reviewed-by: Rob Herring <robh@kernel.org> Thanks for the review. In that series there were two clock bindings relating the pll and gates, There were finally joined in only one binding and driver. This is done in the v3 of this series sent on friday. Thanks for your time in looking also into this new version, Best regards, Sergio Paracuellos
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.yaml new file mode 100644 index 000000000000..ef58411065e4 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mediatek,mt7621-pll.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MT7621 PLL Controller Device Tree Bindings + +maintainers: + - Sergio Paracuellos <sergio.paracuellos@gmail.com> + + +description: | + The PLL Controller provides the cpu clock as well as derived + clock for the bus and the peripherals. + + Each clock is assigned an identifier and client nodes use this identifier + to specify the clock which they consume. + + All these identifiers could be found in: + [1]: <include/dt-bindings/clock/mt7621-clk.h>. + +properties: + compatible: + const: mediatek,mt7621-pll + + "#clock-cells": + description: + The first cell indicates the clock number, see [1] for available + clocks. + const: 1 + + clock-output-names: + maxItems: 3 + +required: + - compatible + - '#clock-cells' + - clock-output-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/mt7621-clk.h> + + pll { + compatible = "mediatek,mt7621-pll"; + #clock-cells = <1>; + clock-output-names = "cpu", "ahb", "apb"; + };
Adds device tree binding documentation for PLL controller in the MT7621 SOC. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> --- .../bindings/clock/mediatek,mt7621-pll.yaml | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.yaml