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Mon, 22 Mar 2021 01:59:20 +0000 From: YunQiang Su To: linux-mips@vger.kernel.org Cc: macro@orcam.me.uk, jiaxun.yang@flygoat.com, f4bug@amsat.org, tsbogend@alpha.franken.de, YunQiang Su , stable@vger.kernel.org Subject: [PATCH v9] MIPS: force use FR=0 for FPXX binaries Date: Mon, 22 Mar 2021 01:59:02 +0000 Message-Id: <20210322015902.18451-1-yunqiang.su@cipunited.com> X-Mailer: git-send-email 2.20.1 X-Originating-IP: [60.247.76.83] X-ClientProxiedBy: HK2PR03CA0047.apcprd03.prod.outlook.com (2603:1096:202:17::17) To HKAPR04MB3956.apcprd04.prod.outlook.com (2603:1096:203:d5::13) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (60.247.76.83) by HK2PR03CA0047.apcprd03.prod.outlook.com (2603:1096:202:17::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3977.10 via Frontend Transport; Mon, 22 Mar 2021 01:59:19 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: bdc021bc-2ad0-44d2-6410-08d8ecd61b72 X-MS-TrafficTypeDiagnostic: HK0PR04MB3314: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1850; 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X-MS-Exchange-AntiSpam-MessageData: 5A7vcw46lTUhLpEkXHsI6BLaMez2ddu7Vf3FQjTgS9ndaL2lzLoY6VTDs9R9IsSSrUsHR2dFQ6/DLJL8u/LBRreDFP4wS0BK7W+YDKOgcAYu5c5ZXTZaN7lAkfPidT2bXq8UUpqro33CDpiyFz9//MIGaRiYvz9KkvtkJF+K0cw2fHS7iKFXEflYqjuFo+BKVmWW9Haj4e+/fIUPwQbxq+P95KAww65+Y+f5CKEmAYlUpX5C6debw/0FO+Lue92BZjOku6FJp+PKL8MvNdT7lq73n7W3eCP63t3MVSNyJKWMtAxyFYUeyalfSFBIfwR78bur8Rd0abAjk3CLrt99BAD1hvhpAcTxDwigChrJxJx2StNbOx33xAXO0Akv5AhElbvMTUOcqLq7NNJ7iD5NSCwW+2qwWnYzVu0DmXmehd4cn5OtXqhWSw7usEBcxKok9fKuSguEgXnVW0gEF2Cp9/KJHlb4StN/Pm6nmXx+KB80wfrg8vSN8K8fyS2rd7X1rwgBNAU6wJW7PUT1NthVe0+od/d27jPHBedMt70cTJ+3OJ1DXcHr0A0Uku6nwaham5tPHEK4uO9Gf1IcxdU0GPVe4n0rxuDUvuIaR63s+OWNYRHIpIuYFPb2EmNPJkStWpO3DMgrESehfIiuVgG70xIFHVWdd6sPmuDCF5IDfqg5WVOEQGN541RCTXZuL0y3pvih2YfBTyATspOLIZMCvVyoM8jBwDhDYBMwYvq9gPcOvdwUGXXrDcFfdMaX6zkh4lryK1UjGYZLbGnY7fJR6DMxTJsxf5NkY6xW2GoNIwmtjvuB3xWSO47jlgUsbtoDxlzNw7h0n9SW7wYTgBK06MEpMKj4holpv/NeAnWdYged86VLAl377JLtXHmnyd3mSbfW056M9Wdv2CRwnQZR73MbkfFvF6YijiDKnsupoGdLs1QCd2xvc0UojHfRpSnJpKMsH65WWn/vGJ6VvCRrkrFWsz5uk5aRjKZ6cc1pDBcoUKHrMXHjCHE3IgnD+cMx3YaUTkHqCTuzQnsPpClUQJrAmbdKPZwQkwWUqoCeR8YKPDRkZj4Ef4FbmkK/gXWsc2FbxlVw9Px/+UKGuhWPOqRJGU3rzF/2qmYgUXdeVJ3keGmkgvjf+nW3R51dnQxWTIZuWmp6wnNOmdAATBiBb3s8HNTWjNpYtwYFOeEcU3ghKGEg9X4B37VUZC7JUCsRZRaMeaovi3oEGOh2g4cbmzBEH6aQrltXIt4uBjYq75ItOrOh5nX2Op0ZsLt9a83wFtl05fHRvETVerZpBZI/AKIf1yh8DVoJkW6xLdQsrZXNR58aiHtIMA64TjNcHpMo X-OriginatorOrg: cipunited.com X-MS-Exchange-CrossTenant-Network-Message-Id: bdc021bc-2ad0-44d2-6410-08d8ecd61b72 X-MS-Exchange-CrossTenant-AuthSource: HKAPR04MB3956.apcprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Mar 2021 01:59:20.2863 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: e31cf5b5-ee69-4d5f-9c69-edeeda2458c0 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Ux25FASL0YREdmjYUwPYoOfEVla4IliIcrScJzO4jWyKwspMkSFXzKLFedKTHH2TLTEeieToL3Bz5ZM3YNNKvovdOd/NtLa4PcyYqgSBjks= X-MS-Exchange-Transport-CrossTenantHeadersStamped: HK0PR04MB3314 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org The MIPS FPU may have 3 mode: FR=0: MIPS I style, all of the FPR are single. FR=1: all 32 FPR can be double. FRE: redirecting the rw of odd-FPR to the upper 32bit of even-double FPR. The binary may have 3 mode: FP32: can only work with FR=0 and FRE mode FPXX: can work with all of FR=0/FR=1/FRE mode. FP64: can only work with FR=1 mode Some binary, for example the output of golang, may be mark as FPXX, while in fact they are FP32. It is caused by the bug of design and linker: Object produced by pure Go has no FP annotation while in fact they are FP32; if we link them with the C module which marked as FPXX, the result will be marked as FPXX. If these fake-FPXX binaries is executed in FR=1 mode, some problem will happen. In Golang, now we add the FP32 annotation, so the future golang programs won't have this problem. While for the existing binaries, we need a kernel workaround. Currently, FR=1 mode is used for all FPXX binary if O32_FP64 supported is enabled, it makes some wrong behivour of the binaries. Since FPXX binary can work with both FR=1 and FR=0, we force it to use FR=0. Reference: https://web.archive.org/web/20180828210612/https://dmz-portal.mips.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking https://go-review.googlesource.com/c/go/+/239217 https://go-review.googlesource.com/c/go/+/237058 Signed-off-by: YunQiang Su Cc: stable@vger.kernel.org # 4.19+ --- v7->v8->v9: Rollback to use FR=1 for FPXX on R6 CPU. v6->v7: Use FRE mode for pre-R6 binaries on R6 CPU. v5->v6: Rollback to V3, aka remove config option. v4->v5: Fix CONFIG_MIPS_O32_FPXX_USE_FR0 usage: if -> ifdef v3->v4: introduce a config option: CONFIG_MIPS_O32_FPXX_USE_FR0 v2->v3: commit message: add Signed-off-by and Cc to stable. v1->v2: Fix bad commit message: in fact, we are switching to FR=0 arch/mips/kernel/elf.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/arch/mips/kernel/elf.c b/arch/mips/kernel/elf.c index 7b045d2a0b51..554561d5c1f8 100644 --- a/arch/mips/kernel/elf.c +++ b/arch/mips/kernel/elf.c @@ -232,11 +232,16 @@ int arch_check_elf(void *_ehdr, bool has_interpreter, void *_interp_ehdr, * that inherently require the hybrid FP mode. * - If FR1 and FRDEFAULT is true, that means we hit the any-abi or * fpxx case. This is because, in any-ABI (or no-ABI) we have no FPU - * instructions so we don't care about the mode. We will simply use - * the one preferred by the hardware. In fpxx case, that ABI can - * handle both FR=1 and FR=0, so, again, we simply choose the one - * preferred by the hardware. Next, if we only use single-precision - * FPU instructions, and the default ABI FPU mode is not good + * instructions so we don't care about the mode. + * In fpxx case, that ABI can handle all of FR=1/FR=0/FRE mode. + * Here, we need to use FR=0 mode instead of FR=1, because some binaries + * may be mark as FPXX by mistake due to bugs of design and linker: + * The object produced by pure Go has no FP annotation, + * then is treated as any-ABI by linker, although in fact they are FP32; + * if any-ABI object is linked with FPXX object, the result will be mark as FPXX. + * Then the problem happens: run FP32 binaries in FR=1 mode. + * - If we only use single-precision FPU instructions, + * and the default ABI FPU mode is not good * (ie single + any ABI combination), we set again the FPU mode to the * one is preferred by the hardware. Next, if we know that the code * will only use single-precision instructions, shown by single being @@ -248,8 +253,9 @@ int arch_check_elf(void *_ehdr, bool has_interpreter, void *_interp_ehdr, */ if (prog_req.fre && !prog_req.frdefault && !prog_req.fr1) state->overall_fp_mode = FP_FRE; - else if ((prog_req.fr1 && prog_req.frdefault) || - (prog_req.single && !prog_req.frdefault)) + else if (prog_req.fr1 && prog_req.frdefault) + state->overall_fp_mode = cpu_has_mips_r6 ? FP_FR1 : FP_FR0; + else if (prog_req.single && !prog_req.frdefault) /* Make sure 64-bit MIPS III/IV/64R1 will not pick FR1 */ state->overall_fp_mode = ((raw_current_cpu_data.fpu_id & MIPS_FPIR_F64) && cpu_has_mips_r2_r6) ?