From patchwork Tue Nov 23 07:49:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Pei X-Patchwork-Id: 12633541 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F195EC4167B for ; Tue, 23 Nov 2021 07:50:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234427AbhKWHxb (ORCPT ); Tue, 23 Nov 2021 02:53:31 -0500 Received: from mail.loongson.cn ([114.242.206.163]:52098 "EHLO loongson.cn" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S234421AbhKWHxa (ORCPT ); Tue, 23 Nov 2021 02:53:30 -0500 Received: from localhost.localdomain (unknown [111.9.175.10]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9AxF+genZxh3IgAAA--.1089S5; Tue, 23 Nov 2021 15:50:08 +0800 (CST) From: Huang Pei To: Thomas Bogendoerfer , ambrosehua@gmail.com Cc: Bibo Mao , Andrew Morton , linux-mips@vger.kernel.org, linux-arch@vger.kernel.org, linux-mm@kvack.org, Jiaxun Yang , Paul Burton , Li Xuefeng , Yang Tiezhu , Gao Juxin , Fuxin Zhang , Huacai Chen Subject: [PATCH 3/6] MIPS: rework local_t operation on MIPS64 Date: Tue, 23 Nov 2021 15:49:24 +0800 Message-Id: <20211123074927.12461-4-huangpei@loongson.cn> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20211123074927.12461-1-huangpei@loongson.cn> References: <20211123074927.12461-1-huangpei@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf9AxF+genZxh3IgAAA--.1089S5 X-Coremail-Antispam: 1UD129KBjvJXoWxZr1ktrW5Ww4UArWrCFW7Arb_yoWrurWrpF srCan7KrWqvF4fA3Z7ZF4Svr13Wr4fGrWYkF1qvrWvy3W8t3W8ZrZ3KanYyrykZFZ8X3W8 XFW7ur15X3ZrA3DanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUPY14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JrWl82xGYIkIc2 x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F4UJw A2z4x0Y4vEx4A2jsIE14v26r4UJVWxJr1l84ACjcxK6I8E87Iv6xkF7I0E14v26rxl6s0D M2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjx v20xvE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1l F7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7M4IIrI8v6xkF7I0E8cxan2 IY04v7MxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAF wI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUtVW8ZwCIc4 0Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AK xVWxJVW8Jr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r 4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x0JUd8n5U UUUU= X-CM-SenderInfo: xkxd0whshlqz5rrqw2lrqou0/ Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org +. use "daddu/dsubu" for long int on MIPS64 instead of "addu/subu" +. remove "asm/war.h" since R10000_LLSC_WAR became a config option +. clean up Suggested-by: "Maciej W. Rozycki" Signed-off-by: Huang Pei --- arch/mips/include/asm/asm.h | 18 ++++++++++ arch/mips/include/asm/local.h | 62 +++++++++-------------------------- 2 files changed, 33 insertions(+), 47 deletions(-) diff --git a/arch/mips/include/asm/asm.h b/arch/mips/include/asm/asm.h index 2f8ce94ebaaf..f3302b13d3e0 100644 --- a/arch/mips/include/asm/asm.h +++ b/arch/mips/include/asm/asm.h @@ -19,6 +19,7 @@ #include #include +#include #ifndef __VDSO__ /* @@ -211,6 +212,8 @@ symbol = value #define LONG_SUB sub #define LONG_SUBU subu #define LONG_L lw +#define LONG_LL ll +#define LONG_SC sc #define LONG_S sw #define LONG_SP swp #define LONG_SLL sll @@ -236,6 +239,8 @@ symbol = value #define LONG_SUB dsub #define LONG_SUBU dsubu #define LONG_L ld +#define LONG_LL lld +#define LONG_SC scd #define LONG_S sd #define LONG_SP sdp #define LONG_SLL dsll @@ -320,6 +325,19 @@ symbol = value #define SSNOP sll zero, zero, 1 +/* + * Using a branch-likely instruction to check the result of an sc instruction + * works around a bug present in R10000 CPUs prior to revision 3.0 that could + * cause ll-sc sequences to execute non-atomically. + */ +#ifdef CONFIG_WAR_R10000_LLSC +# define SC_BEQZ beqzl +#elif MIPS_ISA_REV >= 6 +# define SC_BEQZ beqzc +#else +# define SC_BEQZ beqz +#endif + #ifdef CONFIG_SGI_IP28 /* Inhibit speculative stores to volatile (e.g.DMA) or invalid addresses. */ #include diff --git a/arch/mips/include/asm/local.h b/arch/mips/include/asm/local.h index ecda7295ddcd..c1e109357110 100644 --- a/arch/mips/include/asm/local.h +++ b/arch/mips/include/asm/local.h @@ -7,7 +7,7 @@ #include #include #include -#include +#include typedef struct { @@ -31,34 +31,18 @@ static __inline__ long local_add_return(long i, local_t * l) { unsigned long result; - if (kernel_uses_llsc && IS_ENABLED(CONFIG_WAR_R10000_LLSC)) { - unsigned long temp; - - __asm__ __volatile__( - " .set push \n" - " .set arch=r4000 \n" - __SYNC(full, loongson3_war) " \n" - "1:" __LL "%1, %2 # local_add_return \n" - " addu %0, %1, %3 \n" - __SC "%0, %2 \n" - " beqzl %0, 1b \n" - " addu %0, %1, %3 \n" - " .set pop \n" - : "=&r" (result), "=&r" (temp), "=m" (l->a.counter) - : "Ir" (i), "m" (l->a.counter) - : "memory"); - } else if (kernel_uses_llsc) { + if (kernel_uses_llsc) { unsigned long temp; __asm__ __volatile__( " .set push \n" " .set "MIPS_ISA_ARCH_LEVEL" \n" - __SYNC(full, loongson3_war) " \n" - "1:" __LL "%1, %2 # local_add_return \n" - " addu %0, %1, %3 \n" - __SC "%0, %2 \n" - " beqz %0, 1b \n" - " addu %0, %1, %3 \n" + __SYNC(full, loongson3_war) " \n" + "1:" __stringify(LONG_LL) " %1, %2 \n" + " "__stringify(LONG_ADDU) " %0, %1, %3 \n" + " "__stringify(LONG_SC) " %0, %2 \n" + " "__stringify(SC_BEQZ) " %0, 1b \n" + " "__stringify(LONG_ADDU) " %0, %1, %3 \n" " .set pop \n" : "=&r" (result), "=&r" (temp), "=m" (l->a.counter) : "Ir" (i), "m" (l->a.counter) @@ -80,34 +64,18 @@ static __inline__ long local_sub_return(long i, local_t * l) { unsigned long result; - if (kernel_uses_llsc && IS_ENABLED(CONFIG_WAR_R10000_LLSC)) { - unsigned long temp; - - __asm__ __volatile__( - " .set push \n" - " .set arch=r4000 \n" - __SYNC(full, loongson3_war) " \n" - "1:" __LL "%1, %2 # local_sub_return \n" - " subu %0, %1, %3 \n" - __SC "%0, %2 \n" - " beqzl %0, 1b \n" - " subu %0, %1, %3 \n" - " .set pop \n" - : "=&r" (result), "=&r" (temp), "=m" (l->a.counter) - : "Ir" (i), "m" (l->a.counter) - : "memory"); - } else if (kernel_uses_llsc) { + if (kernel_uses_llsc) { unsigned long temp; __asm__ __volatile__( " .set push \n" " .set "MIPS_ISA_ARCH_LEVEL" \n" - __SYNC(full, loongson3_war) " \n" - "1:" __LL "%1, %2 # local_sub_return \n" - " subu %0, %1, %3 \n" - __SC "%0, %2 \n" - " beqz %0, 1b \n" - " subu %0, %1, %3 \n" + __SYNC(full, loongson3_war) " \n" + "1:" __stringify(LONG_LL) " %1, %2 \n" + " "__stringify(LONG_SUBU) " %0, %1, %3 \n" + " "__stringify(LONG_SC) " %0, %2 \n" + " "__stringify(SC_BEQZ) " %0, 1b \n" + " "__stringify(LONG_SUBU) " %0, %1, %3 \n" " .set pop \n" : "=&r" (result), "=&r" (temp), "=m" (l->a.counter) : "Ir" (i), "m" (l->a.counter)