From patchwork Mon Feb 21 14:55:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 12753750 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0411C433EF for ; Mon, 21 Feb 2022 14:55:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378500AbiBUO4P (ORCPT ); Mon, 21 Feb 2022 09:56:15 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:47254 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378499AbiBUO4P (ORCPT ); Mon, 21 Feb 2022 09:56:15 -0500 Received: from out4-smtp.messagingengine.com (out4-smtp.messagingengine.com [66.111.4.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6E15217AAD; Mon, 21 Feb 2022 06:55:51 -0800 (PST) Received: from compute3.internal (compute3.nyi.internal [10.202.2.43]) by mailout.nyi.internal (Postfix) with ESMTP id 92E875C0211; Mon, 21 Feb 2022 09:55:50 -0500 (EST) Received: from mailfrontend1 ([10.202.2.162]) by compute3.internal (MEProxy); Mon, 21 Feb 2022 09:55:50 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; h= cc:cc:content-transfer-encoding:date:date:from:from:in-reply-to :in-reply-to:message-id:mime-version:references:reply-to:sender :subject:subject:to:to; s=fm1; bh=CGhvsw+LhTgD6aZuUFtqqU1Kc3kIvE iqCXe0yRe6810=; b=e4gBrijTOZhpcNy+jnhFPC0M3cR5xv/xVK+BSjrnefBwqq SFusBz1p7/d22M8zErvkzVUZuhZL/Kn4aVsObOPAckG9arsvxG9OH9fxJkDGJ/mh Aae4VRiKLfJgF7GgqDbFtk6CiHUCUnLx3wwquqWWUgl77vxYj1b8TncUXHXPLXEe twShpKTlddijxWNBNPlRiBo3sU76wKQIrUh3WombyMvL1YnrmtQ7bgAldd5dH/Mt GuIjzBIDrHX9GFjvGXwnt9VIU7vn9aBBh1rXvXUxs5dLEmTeHqwN76fiDiq7KQ+c fALbazbPEhzJ229TsG19hQ14L9ekm2CX/ThSwwCg== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding:date:date :from:from:in-reply-to:in-reply-to:message-id:mime-version :references:reply-to:sender:subject:subject:to:to:x-me-proxy :x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s=fm2; bh=CGhvsw +LhTgD6aZuUFtqqU1Kc3kIvEiqCXe0yRe6810=; b=C1toCK7qAAJFyiRrFibt9+ 57z9FhqcL4Xvbg/sQ7+RAz/Ed895TTNAh3ZAEhu0bylS4xyNpTB0hf+1VLi4XNzk Wn2cq2QB1sNAY+VbegcQ2F3VfusZ7f9O00Dbtng61dNk/9xAu9X9KIU1twshDgWT u61YULPepO6EGCl9jHJkt+T1w35l14Gys4Jvel4sQRa1mBXK1ssQaB4tDDmrv+MQ w1Uhb5qygqANjNTX0N635wNgK/8lIwRpZRqNX6vLcBIJsCDPvwGXORwQ48jnnEnF Q6Wk8gMmzTItyY5+BYEwrc6jYM9LOOHUaB10RDe2kRPz6i6n9RZSVaDDp2LeD4pA == X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvvddrkeeigdeikecutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecunecujfgurhephffvufffkffojghfggfgsedtkeertd ertddtnecuhfhrohhmpeflihgrgihunhcujggrnhhguceojhhirgiguhhnrdihrghnghes fhhlhihgohgrthdrtghomheqnecuggftrfgrthhtvghrnhepjeeihffgteelkeelffduke dtheevudejvdegkeekjeefhffhhfetudetgfdtffeunecuvehluhhsthgvrhfuihiivgep tdenucfrrghrrghmpehmrghilhhfrhhomhepjhhirgiguhhnrdihrghnghesfhhlhihgoh grthdrtghomh X-ME-Proxy: Received: by mail.messagingengine.com (Postfix) with ESMTPA; Mon, 21 Feb 2022 09:55:49 -0500 (EST) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, chenhuacai@kernel.org, tsbogend@alpha.franken.de, macro@orcam.me.uk, Jiaxun Yang Subject: [RFC PATCH 1/3] MIPS: Loongson64: Clearify IO barriers Date: Mon, 21 Feb 2022 14:55:29 +0000 Message-Id: <20220221145531.10479-2-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220221145531.10479-1-jiaxun.yang@flygoat.com> References: <20220221145531.10479-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Remove CPU_HAS_WB from Kconfig as all Loongson64 processors don't have R3000 style write buffer. This is likely to be a legacy of Loongson 2E's Bonito64. Remove Loongson64 from war_io_reorder_wmb. Loongson64 never reorders uncached memory access as per user manual of GS464, LS3A2000 and LS3A3000. It was intruduced due to a misunderstanding of Store Fill Buffer. Signed-off-by: Jiaxun Yang --- arch/mips/Kconfig | 1 - arch/mips/include/asm/io.h | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 058446f01487..6d2e97342723 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -487,7 +487,6 @@ config MACH_LOONGSON64 select BOARD_SCACHE select CSRC_R4K select CEVT_R4K - select CPU_HAS_WB select FORCE_PCI select ISA select I8259 diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index 6f5c86d2bab4..065e1ab6401a 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -219,7 +219,7 @@ void iounmap(const volatile void __iomem *addr); #define ioremap_wc(offset, size) \ ioremap_prot((offset), (size), boot_cpu_data.writecombine) -#if defined(CONFIG_CPU_CAVIUM_OCTEON) || defined(CONFIG_CPU_LOONGSON64) +#if defined(CONFIG_CPU_CAVIUM_OCTEON) #define war_io_reorder_wmb() wmb() #else #define war_io_reorder_wmb() barrier()