diff mbox series

MIPS: Octeon: fix typo in comment

Message ID 20220521111145.81697-65-Julia.Lawall@inria.fr (mailing list archive)
State Accepted
Commit f998c204a19a3d49a49adfd7172fb15c3f0484ea
Headers show
Series MIPS: Octeon: fix typo in comment | expand

Commit Message

Julia Lawall May 21, 2022, 11:11 a.m. UTC
Spelling mistake (triple letters) in comment.
Detected with the help of Coccinelle.

Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr>

---
 arch/mips/pci/pcie-octeon.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Thomas Bogendoerfer May 23, 2022, 9:16 a.m. UTC | #1
On Sat, May 21, 2022 at 01:11:15PM +0200, Julia Lawall wrote:
> Spelling mistake (triple letters) in comment.
> Detected with the help of Coccinelle.
> 
> Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr>
> 
> ---
>  arch/mips/pci/pcie-octeon.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/mips/pci/pcie-octeon.c b/arch/mips/pci/pcie-octeon.c
> index 50a3394a9d25..c9edd3fb380d 100644
> --- a/arch/mips/pci/pcie-octeon.c
> +++ b/arch/mips/pci/pcie-octeon.c
> @@ -895,7 +895,7 @@ static int __cvmx_pcie_rc_initialize_gen1(int pcie_port)
>  	mem_access_subid.s.nsw = 0;	/* Enable Snoop for Writes. */
>  	mem_access_subid.s.ror = 0;	/* Disable Relaxed Ordering for Reads. */
>  	mem_access_subid.s.row = 0;	/* Disable Relaxed Ordering for Writes. */
> -	mem_access_subid.s.ba = 0;	/* PCIe Adddress Bits <63:34>. */
> +	mem_access_subid.s.ba = 0;	/* PCIe Address Bits <63:34>. */
>  
>  	/*
>  	 * Setup mem access 12-15 for port 0, 16-19 for port 1,

applied to mips-next.

Thomas.
diff mbox series

Patch

diff --git a/arch/mips/pci/pcie-octeon.c b/arch/mips/pci/pcie-octeon.c
index 50a3394a9d25..c9edd3fb380d 100644
--- a/arch/mips/pci/pcie-octeon.c
+++ b/arch/mips/pci/pcie-octeon.c
@@ -895,7 +895,7 @@  static int __cvmx_pcie_rc_initialize_gen1(int pcie_port)
 	mem_access_subid.s.nsw = 0;	/* Enable Snoop for Writes. */
 	mem_access_subid.s.ror = 0;	/* Disable Relaxed Ordering for Reads. */
 	mem_access_subid.s.row = 0;	/* Disable Relaxed Ordering for Writes. */
-	mem_access_subid.s.ba = 0;	/* PCIe Adddress Bits <63:34>. */
+	mem_access_subid.s.ba = 0;	/* PCIe Address Bits <63:34>. */
 
 	/*
 	 * Setup mem access 12-15 for port 0, 16-19 for port 1,